SoC Design Verification Lead - Santa Clara, CA, United States
$200,000 - $300,000 USD yearly
Originally posted 15 September 2026 by the employer.
Velaura AI Physical AI SoC
About the role
This role leads system-level verification for Velaura AI, owning the SoC verification plan from sign-off through tape-out. You will focus on the Physical AI SoC, covering boot and root of trust, clock and reset topology, low power behavior, and IO and memory subsystems.
What you'll do
- Own the SoC level verification strategy, plan, and execution for the Physical AI SoC.
- Build and lead a team of SoC verification engineers, setting technical direction.
- Define the SoC verification architecture and environment, and stay hands-on.
- Coordinate verification across boot and security, clock and reset, low power, and IO and memory subsystems.
- Define sign-off criteria and coverage goals, and drive closure through tape out.
- Track and report verification progress, coverage, and risk to engineering leadership.
What you'll need
- 12 or more years in design verification, including significant SoC level experience.
- Experience leading SoC verification across multiple projects through sign-off and tape out.
- Experience building and leading a team of verification engineers.
- Experience with SystemVerilog, UVM, C, C++, and coverage driven verification at system level.
- Experience managing simulation flows on CPU based SoCs such as ARM or RISC-V.
- Knowledge of IO and memory subsystem IP such as PCIe and LPDDR5 or LPDDR6.
- Experience verifying boot and root of trust, clock and reset topology, and low power behavior at system level, including CDC, RDC, and UPF based flows.
Nice to have
- Experience with HW and SW co verification and pre silicon software bring up.
- Experience with emulation and FPGA prototyping at SoC level.
- Experience with one or more of ISO 26262, IEC 61508, IEC 61511, or ISO 13849.
- Experience verifying QoS, latency sensitive, or real time systems.
- Experience with post silicon bring up, debug, and root cause analysis.
- Experience building a verification team at an early stage company.
- Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
- Experience using AI assisted verification workflows to improve productivity and coverage.
Skills: SoC level verification, SystemVerilog, UVM, coverage driven verification, low power behavior
This role has been open 28 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1187
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (1187 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 1187 |
| Open roles in the wider Digital Design & Verification family | 17 | 3167 · 115 employers |
| Median days open | 67 d | 64 d (+3 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: SoC level verification, SystemVerilog, UVM, coverage driven verification, low power behavior
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- AMD · 99 open roles · median 54 d
- NVIDIA · 79 open roles · median 61 d
- Synopsys · 61 open roles · median 30 d
- SiFive · 54 open roles · median 71 d
- Cadence Design Systems · 51 open roles · median 113 d
How we counted: 1187 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.