SoC Design Verification Engineer - Santa Clara, CA, United States
$200,000 - $300,000 USD yearly
Originally posted 15 September 2026 by the employer.
This role focuses on system-level verification of Velaura's Physical AI SoC.
About the role
This role focuses on system-level verification of Velaura's Physical AI SoC, working closely with architects, RTL engineers, software engineers, and system teams to establish confidence in the correctness, performance, reliability, and safety of the design. The scope spans boot and root of trust, clock and reset topology, low power behavior, and IO and memory subsystems.
What you'll do
- Drive verification planning and execution for assigned areas of the Physical AI SoC.
- Build and maintain SoC level simulation environments and flows for CPU based SoCs.
- Verify boot flows, root of trust, security state transitions, and firmware handoff.
- Verify clock and reset topology, power domains, and low power behavior at system level.
- Verify IO and memory subsystem integration including PCIe and LPDDR.
- Run CDC and RDC analysis at SoC level and close findings with design teams.
What you'll need
- 10 or more years in design verification, including significant SoC level experience.
- Experience leading or participating in multiple SoC verification projects, including sign off and tape out.
- Experience with SystemVerilog, UVM, C and C++, and coverage driven verification at system level.
- Experience managing simulation flows on CPU based SoCs such as ARM or RISC-V.
- Knowledge of IO and memory subsystem IP such as PCIe and LPDDR5 or LPDDR6.
- Experience verifying boot sequences and root of trust.
- Experience verifying clock and reset topology at system level, with hands-on use of CDC and RDC tools.
- Experience with low power verification tools and UPF based flows.
Nice to have
- Depth in one or more areas such as security, memory subsystem, interconnect, or power management.
- Experience with HW and SW co verification and pre silicon software bring up.
- Experience with emulation and FPGA prototyping at SoC level.
- Experience with one or more of ISO 26262, IEC 61508, IEC 61511 or ISO 13849.
- Experience verifying QoS, latency sensitive, or real time systems.
- Experience with post silicon bring up, debug, and root cause analysis.
- Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
- Experience using AI assisted verification workflows to improve productivity and coverage.
Skills: SoC level simulation, SystemVerilog, UVM, coverage driven verification, CDC and RDC analysis
This role has been open 28 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1187
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (1187 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 1187 |
| Open roles in the wider Digital Design & Verification family | 17 | 3167 · 115 employers |
| Median days open | 67 d | 64 d (+3 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: SoC level simulation, SystemVerilog, UVM, coverage driven verification, CDC and RDC analysis
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- AMD · 99 open roles · median 54 d
- NVIDIA · 79 open roles · median 61 d
- Synopsys · 61 open roles · median 30 d
- SiFive · 54 open roles · median 71 d
- Cadence Design Systems · 51 open roles · median 113 d
How we counted: 1187 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.