SOC Design Verification Engineer - Irvine, United States
Originally posted 15 October 2026 by the employer.
Join Apple's wireless silicon development team focusing on Power Management Unit, CPU subsystem, DMA, and PCIe verification.
About the role
As a Wireless SOC Design Verification Engineer, you will be responsible for pre-silicon RTL verification at the block, subsystem, and top-level SOC. You will own a meaningful verification scope, taking it from test planning through coverage closure and signoff.
What you'll do
- Take verification scope from test planning through coverage closure and signoff at the block, subsystem, and top-level SOC.
- Build reusable testbenches and verification environments using modern, metric-driven methodology.
- Work closely with architects, designers, and firmware engineers.
- Verify power intent using UPF within your area.
- Explore application of AI-assisted verification for test generation, debug, and coverage closure.
What you'll need
- BS and a minimum of 10 years relevant industry experience.
- Hands-on experience across the verification cycle: test planning, testbench implementation, test creation and debug, and coverage closure.
- Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.
- Solid problem-solving and debugging skills with constrained-random verification.
- Understanding of digital logic design, SOC architecture, and microarchitecture.
Nice to have
- Experience taking at least one ASIC/SOC from concept through tape-out.
- Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment.
- Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols.
- Experience with low-power verification, UPF, boot-up, power-cycling, and HW/FW interaction.
- Experience with SystemVerilog Assertions (SVA) and/or formal tools (e.g., JasperGold).
- Experience defining coverage space and writing coverage models.
- Experience with embedded CPU verification; programming in C/C++ or assembly.
- Scripting in Python or Perl; interest in applying AI/ML to verification workflows.
Skills: SystemVerilog, UVM, constrained-random verification, test planning, coverage closure
This role has been open 1 day — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 1195 |
| Open roles in the wider Digital Design & Verification family | 67 | 3198 · 115 employers |
| Median days open | 9 d | 64 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: SystemVerilog, UVM, constrained-random verification, test planning, coverage closure
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.