SoC Design and Integration Engineer
$121,800 - $182,600 USD yearly
Originally posted 25 September 2026 by the employer.
About the role
This role is for an ASIC engineer responsible for RTL design, flows, and methodology for high-performance ASICs in the latest process nodes for High Performance Compute and AI spaces.
What you'll do
- Execute the architecture and design of SoC according to design protocol.
- Resolve architecture, design, or verification problems using sound ASIC engineering practices.
- Execute design and verification strategies according to ASICs, SoC, and IP core specifications.
- Participate and contribute to design and architecture reviews.
- Identify areas for flow and process improvements through design techniques and automation.
- Provide feedback on Silicon learnings to the process team, design methodology, IP, and SoC design.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field.
- Knowledge in Server/Data Center IPs, protocols, and interfaces.
- Experience in designing arithmetic/computational/machine learning IPs.
- Understanding of design techniques for speed and for power efficiency.
- Experience overseeing definition, design, verification, and documentation for ASIC development.
- Ability to determine architecture design, logic design, large-scale design integration and system simulation.
Nice to have
- Master's degree in Electrical Engineering, Computer Science, or Computer Engineering.
- 5 years of relevant experience in ASIC design, scripting and architecture.
- Experience in designing arithmetic/computational/machine learning IPs.
- Experience in developing tools and scripting for process automation.
Skills: SoC Design and Integration, RTL Design, architecture design, large-scale design integration, machine learning IPs
This role has been open 15 days — well below the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
460
|
Median days open
77 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (460 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 74 | 460 |
| Open roles in the wider Digital Design & Verification family | 385 | 3166 · 114 employers |
| Median days open | 82 d | 77 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: SoC Design and Integration, RTL Design, architecture design, large-scale design integration, machine learning IPs
Who's hiring in this category
- Qualcomm (this employer) · 76 open roles · median 81 d
- NVIDIA · 60 open roles · median 64 d
- AMD · 36 open roles · median 59 d
- Apple · 34 open roles · median 4 d
- Arm Holdings · 27 open roles · median 107 d
- NXP Semiconductors · 21 open roles · median 109 d
How we counted: 460 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.