SOC Debug Engineer
Digital Design & SoC Architecture
$145,600 - $218,400 USD yearly
Originally posted 6 October 2026 by the employer.
This role focuses on SoC platform architectures utilizing RISC-V architecture.
About the role
This role involves defining, modeling, and designing SoC architectures as part of the SoC Platform Architecture team.
What you'll do
- Create highly scalable SoC architecture with expertise in SoC control, boot, reset, timebase management, debug, and micro-controllers.
- Comprehend product requirements to steer generation of proper architecture.
- Perform trade-off analysis in the solution space to produce the most optimal architecture.
- Collaborate with architects, technical leads, hardware, and software engineers to derive architectural solutions.
- Generate detailed architectural specifications and work closely with the design team to implement the architecture.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Proven expertise in debug and security architecture.
- Proven expertise in SoC functional domains such as boot, reset, timebase management, micro-controllers, and clocking.
- Experience with ARM and RISC-V AP architecture.
- Strong foundation of silicon design principles and architectural trade-offs.
- Ability to span and connect levels of abstraction across system-design, high-level languages, OS, HW/SW interface, micro-architecture, and silicon implementation.
- Background in architecture (IP or SoC), and/or front-end design/verification (micro-architecture).
- Demonstrated deep technical knowledge and achievements at the SoC, sub-system or large IP levels as micro-architect or architect.
- Ability to apply appropriate abstractions and quantitative analysis for problem definition and solutions.
- Experience in using, improving, and developing a variety of tools for analysis and modeling, such as functional and performance simulators, and profilers.
- Programming ability for modeling and automation (OOP C++, Python preferred) with experience in software development best practices including reviews, unit-testing, and version control.
Nice to have
- Experience in SoC areas such as boot, timebase management, network, security architecture, reset architecture, and debug architecture.
- Experience with system level control/management with components such as BMC and ECU.
- Experience with SoC architectures including heterogeneous compute, NoC/interconnect, memory-systems, multicore, multi-die, cache hierarchies, shared memory, I/O, coherency, compression, and security.
- Experience with resource and power management.
- Experience with system-level debug.
- Experience with safety, reliability, and high-resilience/high-availability systems.
- Experience with AI & Machine Learning.
- Experience with control and real-time systems.
- Experience with high-level operating systems (e.g., Android, Linux, Windows).
- Experience with real-time operating systems (e.g., Zephyr, FreeRTOS).
- Experience with front-end digital hardware design or verification.
- Experience with ARM system architectures (e.g., Cortex-A, Cortex-R, Cortex-M, CoreSight).
- Experience with high-speed I/O (USB, PCIe, CXL).
- Experience with external memory and storage architectures (e.g., LPDDR, NAND Flash, NOR Flash).
- Experience with networking & connectivity (e.g., Ethernet, WLAN, Cellular, CAN).
- Experience with behavioral, functional, and performance modeling.
- Experience with power and/or performance optimization through simulation & modeling.
- Experience with simulator architectures and frameworks (C++ or Python-based preferred).
- Experience with analytical modeling for performance and power.
Skills: SoC architecture, RISC-V, debug architecture, heterogeneous compute, memory systems
Market context
This role has been open 2 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
461
|
Median days open
76 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (461 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 76 | 461 |
| Open roles in the wider Digital Design & Verification family | 389 | 3175 · 113 employers |
| Median days open | 81 d | 76 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: SoC architecture, RISC-V, debug architecture, heterogeneous compute, memory systems
Who's hiring in this category
- Qualcomm (this employer) · 77 open roles · median 79 d
- NVIDIA · 60 open roles · median 63 d
- AMD · 36 open roles · median 58 d
- Apple · 32 open roles · median 3 d
- Arm Holdings · 27 open roles · median 106 d
- NXP Semiconductors · 21 open roles · median 108 d
How we counted: 461 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.