SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)
$145,600 - $218,400 USD yearly
Originally posted 2 October 2026 by the employer.
This role focuses on end-to-end validation of clock, power, reset, and power-management architectures for AI accelerator platforms.
About the role
This role involves leading end-to-end validation of clock, power, reset, and power-management architectures for AI accelerator platforms. You will drive pre-silicon and post-silicon validation of Clocking infrastructure, PMIC integration, DVFS, and low-power features across complex multi-die AI systems.
What you'll do
- Own end-to-end bare metal framework validation of SoC clock and power architectures.
- Develop validation plans and test strategies for standalone and system-level scenarios.
- Create scalable device drivers, standalone, and system tests using C.
- Debug complex issues on pre-silicon and post-silicon platforms, providing debug direction.
- Automate validation processes, execution, and inference using Python, Perl, and shell.
- Use lab instruments such as multimeters, oscilloscopes, and logic analyzers.
What you'll need
- Bachelor’s degree in engineering (electronics, computer engineering etc.).
- 5 years of relevant experience in SoC validation and/or associated areas.
- Prior work experience in clock/power validation.
- Proficient in C and Python.
- Experienced in using lab instruments (multimeter, oscilloscopes, logic analyzers).
- Exposure to debug tools (JTAG) and knowledge of debug methodology of ARM based SoCs.
Nice to have
- Experience with Cross-Compilers, Linkers, and makefiles.
- Understanding of coherency and concurrency in modern SoC architecture.
- Knowledge of PMIC/prior experience in validating rail power (power measurement tools/setups).
- Knowledge of pre-Silicon validation and debug on FPGA based emulation platforms.
- Knowledge of RTL and HDLs (Verilog/SystemVerilog).
- Prior work experience in a cross-functional matrix work environment.
Skills: SoC validation, post-silicon, clocking, power management, PMIC, AI accelerator
This role has been open 7 days — well below the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
401
|
Median days open
41 d
|
Median salary
$174k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (401 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 34 | 401 |
| Open roles in the wider Silicon Validation & Test family | 132 | 2209 · 111 employers |
| Median days open | 27 d | 41 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $174k |
Skills observed across this category: SoC validation, post-silicon, clocking, power management, PMIC, AI accelerator
Who's hiring in this category
- AMD · 56 open roles · median 51 d
- Micron Technology · 41 open roles · median 35 d
- Qualcomm (this employer) · 33 open roles · median 28 d
- Graphcore · 22 open roles · median 113 d
- NVIDIA · 21 open roles · median 28 d
- Microchip Technology · 20 open roles · median 66 d
How we counted: 401 open Post-Silicon Validation (Silicon Validation) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.