SoC Chip Lead - San Jose, CA, United States
$248,400 USD yearly
Originally posted 7 October 2026 by the employer.
About the role
This role involves leading SoC chip development, focusing on MCMs with FPGA and ASSPs utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures.
What you'll do
- Lead development of MCMs with FPGA and ASSPs utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures.
- Own chip tapeout and chip signoff with full accountability for chip quality.
- Drive cross-functional technical leadership and translate product requirements into priorities and execution paths.
- Partner with architects, RTL engineers, and software teams to evaluate architecture tradeoffs and drive hardware design decisions.
- Own system-level debug spanning floor-planning, power distribution, clocking, timing closure, and SI/PI.
What you'll need
- BS/MS/PhD in Electrical or Computer Engineering with 20+ years of FPGA/SoC design experience.
- Established track record leading programs from concept to tape-out and production release.
- Expertise in SystemVerilog, synthesis, and static timing analysis.
- Deep expertise across SoC domains including High-speed interfaces, System Interconnects, Processor subsystems, and 2.5D/3D packaging and chiplet-based architectures.
- Own system-level functional and performance modeling across SoC subsystems, ensuring RTL correlation and supporting emulation-based pre-silicon validation.
- Define and own DFx methodology including scan, BIST, and manufacturing test from IP to chip level.
Skills: MCMs, 2.5D/3D advanced packaging, chiplet-based architectures, chip tapeout, DFx methodology, performance modeling
This role has been open 2 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
461
|
Median days open
76 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lattice Semiconductor | All employers we track in this specialty (461 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 461 |
| Open roles in the wider Digital Design & Verification family | 20 | 3175 · 113 employers |
| Median days open | 20 d | 76 d (−56 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: MCMs, 2.5D/3D advanced packaging, chiplet-based architectures, chip tapeout, DFx methodology, performance modeling
Who's hiring in this category
- Qualcomm · 77 open roles · median 79 d
- NVIDIA · 60 open roles · median 63 d
- AMD · 36 open roles · median 58 d
- Apple · 32 open roles · median 3 d
- Arm Holdings · 27 open roles · median 106 d
- NXP Semiconductors · 21 open roles · median 108 d
How we counted: 461 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.