SoC Architecture - IP Power
$140,000 - $210,000 USD yearly
Originally posted 2 July 2026 by the employer.
Focus on power estimation, analysis, and architecture optimizations across NOC, System Cache, and System MMU IPs.
About the role
This role involves working with hardware designers to gather power estimation of SoC infrastructure hardware IPs, analyze power data, identify architectural and micro-architectural limitations, and propose fixes and optimizations. Focus areas span platform infrastructure components including Interconnect (NOC), System Cache, Memory controllers, and System MMU.
What you'll do
- Gather power estimation data for SoC infrastructure hardware IPs and perform detailed technical analysis. - Identify architectural and micro-architectural bugs and limitations, proposing targeted fixes and power optimizations. - Coordinate with domain leads to align infrastructure deployment plans with product requirements. - Evaluate hardware architecture and hardware-software feature trade-offs across the silicon hardware design flow.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 4+ years of ASIC design, verification, validation, integration, or related work experience (or Master's with 3+ years, or PhD with 2+ years). - Experience in system power architecture and design, alongside exposure to power estimation flows. - Understanding of computer architecture and end-to-end ASIC design flows. - Knowledge of SoC and Infrastructure IP hardware architecture, specifically NOC, SMMU, and caches. - Exposure to interconnect protocols. - Familiarity with a programming language for automation.
Nice to have
- Exposure to Quality of Service, Clocks, Power management, Security, and Debug architectures and their respective software interfaces. - Knowledge of industry standard Interconnect Protocol and IO Devices Protocol. - Understanding of HW-SW interfaces and firmware. - Experience with post-silicon flows and debugs.
Skills: HW architecture, silicon HW end-to-end design flow, system power architecture, NOC, SMMU, Interconnect Protocol
This role has been open 110 days — well above the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
475
|
Median days open
77 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (475 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 79 | 475 |
| Open roles in the wider Digital Design & Verification family | 407 | 3283 · 116 employers |
| Median days open | 84 d | 77 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: HW architecture, silicon HW end-to-end design flow, system power architecture, NOC, SMMU, Interconnect Protocol
Who's hiring in this category
- Qualcomm (this employer) · 76 open roles · median 87 d
- NVIDIA · 55 open roles · median 70 d
- Apple · 38 open roles · median 13 d
- AMD · 34 open roles · median 63 d
- Arm Holdings · 27 open roles · median 118 d
- Micron Technology · 22 open roles · median 110 d
How we counted: 475 open SoC/Chip Architecture (SOC Architecture) roles from 66 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.