NOC IP Digital Design Engineer - Bangalore (India), India

Originally posted 19 August 2026 by the employer.

Own analog IP co-integration strategy for an automotive microcontroller platform.

About the role

You will ensure analog IPs fit within the clock, reset, and power domain framework, and drive the floorplan strategy for analog IP placement.

What you'll do

• Own the chip-level integration strategy for all analog IPs, ensuring proper fit within clock, reset, and power domains.
• Drive the floorplan strategy for analog IP placement and define reference distribution architecture, focusing on ADC and SMIF interface integrity.
• Perform early model-based and transistor-level simulation for power and signal integrity verification.
• Define noise budget allocation across analog IPs and establish co-existence rules for analog-digital IP proximity.
• Review analog IP scalability decisions across product variants for efficient platform reuse.
• Serve as technical lead for analog IP design reviews and chip integration sign-off.
• Work with PHY and PMIC vendors to verify electrical compatibility through model-based verification.
• Maintain technical architecture documentation in compliance with ISO 26262 requirements.

What you'll need

• Bachelor's or Master's degree in Electrical Engineering or related field.
• At least 10 years of industry experience in semiconductor development with a focus on analog circuit design and mixed-signal subsystem integration.
• Knowledge of analog IP development (ADCs, data converters, SMIF interfaces, LDOs, bandgap references) and their chip-level integration requirements.
• Experience with model-based and transistor-level simulation for power and signal integrity analysis.
• Understanding of floorplan constraints for analog IP placement, guard ring requirements, substrate coupling, and noise injection budgets.
• Familiarity with PHY and PMIC compatibility assessment at chip and system level.
• Familiarity with ISO 26262 documentation standards.

Nice to have

• Defined analog IP integration strategies including reference distribution architecture and floorplan placement recommendations for ADC-heavy platforms.
• Hands-on simulation experience for AMS co-existence analysis (noise injection budgets, aggressor-victim assessment, substrate coupling).
• Reviewed analog IP scalability decisions (e.g., ADC channel count, SMIF interface count) across a platform product family.
• Participated in analog IP design reviews and chip integration reviews across the full IP development lifecycle.
• Worked with PHY and PMIC vendors on model-based electrical compatibility verification.

Skills: analog IPs, clock, reset, power domain, floorplan strategy, ADC, signal integrity, ISO 26262