$133,900 - $200,900 USD yearly
Originally posted 22 September 2026 by the employer.
About the role
This role focuses on signal integrity and power integrity within the Central Hardware System team for server projects. You will collaborate with IC, package, and PCB designers to optimize overall system performance prior to package tape-out.
What you'll do
- Perform package extraction for time-domain and frequency-domain analysis.
- Execute system-level analysis for DDR, SerDes, and PDN.
- Develop design guidelines for package and PCB design.
- Work with substrate designers to verify system-level constraints prior to package tape-out.
- Collaborate with PHY owners on IP specifications (including LP6, PCIe, and 224G) and assess the impact of ball assignment on system performance.
- Create technical documentation and presentations for cross-functional teams.
What you'll need
- Bachelor's degree in Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a related field with 2+ years of system, package design, or technology engineering experience (or Master's degree with 1+ year, or a PhD).
- Experience evaluating signal integrity, power integrity, or system-level constraints.
- Experience collaborating across package, IC, or PCB design teams.
Nice to have
- 3+ years of experience in DDR/SerDes package, PCB, or system design related to compute, automotive, or server projects.
- Solid background in electromagnetics, transmission line theory, and crosstalk.
- Proficiency in field solvers such as HFSS, Q3D, Sentinel-PSI, or Clarity.
- Experience with circuit simulation tools such as ADS and Hspice.
- Working knowledge of layout tools such as Cadence Allegro, APD, SiP, or Mentor Xpedition.
- Experience with design specifications such as LPDDRx, PCIe, or Xlink, or scripting in Matlab.
Skills: SIPI, DDR, SerDes, PDN, HFSS, transmission line
More semiconductor jobs: Qualcomm jobs · Signal integrity jobs · San Diego jobs
First seen in our index 51 days ago, below the 58-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
256
|
Median days since first seen
58 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (256 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 256 |
| Open roles in the wider Analog & Mixed-Signal family | 77 | 1543 · 116 employers |
| Median days since first seen | 85 d | 58 d (−27 d vs this employer) |
| Median salary (USD postings) | n/a | $206k |
Skills observed across this category: SIPI, DDR, SerDes, PDN, HFSS, transmission line
Who's hiring in this category
- Synopsys · 41 open roles · median 40 d
- AMD · 21 open roles · median 48 d
- Cadence Design Systems · 21 open roles · median 156 d
- NVIDIA · 18 open roles · median 217 d
- Qualcomm (this employer) · 17 open roles · median 90 d
- Micron Technology · 11 open roles · median 50 d
How we counted: 256 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 53 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Analog & Mixed-Signal family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.