Silicon Validation Engineer, Software - San Jose, United States
Originally posted 3 September 2026 by the employer.
About the role
This role involves developing firmware and low-level software to validate AI/ML accelerator ASICs across their lifecycle, from pre-silicon emulation and FPGA prototyping through post-silicon bring-up, characterization, and production ramp. You will build validation firmware, test content, and automation to prove silicon functionality and debug hardware in the lab.
What you'll do
- Develop and own low-level validation firmware in C/C++ that runs across emulation and physical silicon. - Drive early bring-up of first silicon, including boot, initialization, and feature enablement. - Perform deep-dive debug of silicon issues spanning firmware, RTL, electrical, protocol, and system levels. - Build firmware infrastructure, including hardware abstraction layers (HALs) and low-level device drivers. - Develop and extend validation automation, result-capture, and regression frameworks (CI/CD). - Author firmware-driven test plans and define coverage metrics across IP blocks and subsystems.
What you'll need
- Proficiency in C/C++ for firmware and bare-metal development, plus Python for validation automation and scripting. - Understanding of SoC/computer architecture (CPU cores, memory subsystems, caches, interconnects). - Solid low-level/embedded fundamentals: bootloaders, hardware abstraction layers, device drivers, register/interrupt programming, and bare-metal or RTOS environments. - Knowledge and familiarity developing and debugging in Linux environments. - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Nice to have
- 2+ years of experience developing firmware / embedded software for ASICs or SoCs. - Hands-on experience with silicon bring-up and low-level debug. - Experience with JTAG and debuggers (e.g., Lauterbach/GDB) and serial/UART debug consoles. - Experience across both pre-silicon (emulation, FPGA, RTL simulation) and post-silicon (lab bring-up, characterization) environments. - Experience with one or more high-speed interfaces: PCIe, DDR/LPDDR/HBM, SerDes, or die-to-die / chiplet interconnect. - Experience building test/validation automation and regression frameworks (CI/CD). - RTOS experience (FreeRTOS, Zephyr, NuttX) or RISC-V firmware development. - Familiarity with platform/system firmware (UEFI, ACPI, BMC, BIOS). - Ability to read RTL (Verilog/SystemVerilog) and debug in simulation. - Hands-on lab instrumentation experience (oscilloscopes, logic/protocol analyzers, BERTs) and signal-integrity awareness.
Skills: low-level validation firmware, post-silicon bring-up, silicon debug, hardware abstraction layers, JTAG
This role has been open 42 days — slightly above the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
412
|
Median days open
41 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (412 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 412 |
| Open roles in the wider Silicon Validation & Test family | 10 | 2220 · 112 employers |
| Median days open | 128 d | 41 d (+87 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: low-level validation firmware, post-silicon bring-up, silicon debug, hardware abstraction layers, JTAG
Who's hiring in this category
- AMD · 58 open roles · median 41 d
- Micron Technology · 39 open roles · median 37 d
- Qualcomm · 37 open roles · median 27 d
- NVIDIA · 25 open roles · median 22 d
- Graphcore · 21 open roles · median 120 d
- Microchip Technology · 20 open roles · median 70 d
How we counted: 412 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.