Silicon Validation Engineer - Mountain View, CA, United States
$250,000 - $300,000 USD yearly
Originally posted 22 October 2026 by the employer.
About the role
Own silicon validation end to end for an AI accelerator, starting in emulation and FPGA prototyping before tapeout, bringing up first silicon in the lab, and continuing through to production.
What you'll do
- Create validation plans for AI accelerator silicon, spanning pre-silicon through production. - Build validation environments, including validation firmware, applications, test content, and silicon diagnostics. - Develop test automation that scales execution and automated triage across silicon samples, tests, and test hours. - Run pre-silicon validation on emulation and FPGA prototyping platforms. - Lead silicon and system bring-up from first power-on through full post-silicon validation, including functional validation, power and performance characterization, and characterization across process, voltage, and temperature (PVT). - Debug and root-cause issues across emulation, silicon, system hardware, firmware, and software, and support production ramp activities including system-level test (SLT), board and system test, field deployment, and RMA analysis.
What you'll need
- 5+ years of experience in silicon validation, post-silicon bring-up, or a related field on complex SoCs or accelerators. - Coding skills in C, C++, and Python, alongside embedded and/or bare-metal programming experience. - Hands-on experience with pre-silicon validation on emulation platforms (Palladium, ZeBu, Veloce) and FPGA prototyping platforms (Protium, HAPS, or equivalent). - Proven silicon and system bring-up experience, from first chip power-on through full post-silicon validation. - Fluency with debug tools including waveform debug (Verdi, FSDB), JTAG debuggers, oscilloscopes, and logic analyzers. - Expertise in one or more areas: AI workloads, kernel operators, and collectives; PCIe Gen5/6/7; DRAM and HBM; power and power management; silicon and system performance; 112G/224G SerDes and networking (including RDMA); silicon debug and RAS features; or secure boot.
Skills: silicon validation, bring-up, AI accelerator, emulation, oscilloscope
This role has been open 0 days — well below the 44-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
414
|
Median days open
44 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | DensityAI | All employers we track in this specialty (414 roles · 62 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 414 |
| Open roles in the wider Silicon Validation & Test family | 4 | 2256 · 113 employers |
| Median days open | 0 d | 44 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: silicon validation, bring-up, AI accelerator, emulation, oscilloscope
Who's hiring in this category
- AMD · 54 open roles · median 48 d
- Qualcomm · 38 open roles · median 28 d
- Micron Technology · 37 open roles · median 44 d
- NVIDIA · 25 open roles · median 23 d
- Microchip Technology · 22 open roles · median 73 d
- Graphcore · 21 open roles · median 126 d
How we counted: 414 open Post-Silicon Validation (Silicon Validation) roles from 62 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.