Silicon Packaging Design Architect - Arizona, Phoenix, United States
$164,470 - $311,890 USD yearly
Originally posted 30 September 2026 by the employer. Relisted by the employer on 6 October 2026.
This role focuses on 3D IC designs.
About the role
This role involves driving end-to-end package solutions for physical, electrical, and cost requirements. You will work on advanced packaging solutions that enable Intel's silicon technologies, specifically focusing on 3D IC designs.
What you'll do
- Translate product requirements into detailed package architecture specifications.
- Drive technology tradeoff decisions to ensure silicon packages conform to electrical, mechanical, thermal, and reliability standards.
- Collaborate with silicon, hardware, and package teams to deliver high-quality package solutions and overcome roadblocks.
- Oversee the end-to-end package development process, including design, procedures, and continuous improvements to quality standards.
- Troubleshoot packaging designs and resolve issues related to materials and processes, providing innovative and cost-effective solutions.
- Implement co-design strategies between silicon and board design teams to optimize product performance and cost.
- Collaborate with EDA partners to advance package design tools and optimize design methods.
What you'll need
- Bachelor's degree in electrical engineering, mechanical engineering, chemical engineering, materials science, or a STEM related role with 6+ years of experience OR Master's degree with 4+ years of experience OR Ph.D. with 2+ years of experience.
- 2+ years of hands-on experience in semiconductor fabrication, chip assembly, or packaging.
- Experience in electromagnetic simulation tools such as Mentor, Cadence tools, SPICE, Ansys tools, or similar platforms.
- Experience with Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity) and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).
- In-depth knowledge of assembly processes, test methodologies, and characterization techniques.
- US Citizenship required.
- Ability to obtain and maintain US Government TS/SCI Security Clearance with Polygraph.
Nice to have
- Active US Government TS/SCI Security Clearance with Polygraph.
- 10+ years of experience with knowledge in Package, PCB design, or IC digital design.
- Experience in troubleshooting and optimizing packaging designs for cost and quality.
- Experience in semiconductor fabrication and packaging processes.
- Experience collaborating with multidisciplinary teams.
- Experience with technology trade-off decisions to ensure high-quality package outputs.
Skills: package solutions, package architecture specifications, 3D IC designs, co-design strategies, EDA partners
This role has been open 9 days — well below the 101-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
43
|
Median days open
101 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (43 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 43 |
| Median days open | 26 d | 101 d (−75 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: package solutions, package architecture specifications, 3D IC designs, co-design strategies, EDA partners
Who's hiring in this category
- Marvell Technology · 5 open roles · median 37 d
- Qualcomm · 5 open roles · median 101 d
- Intel Corporation (this employer) · 4 open roles · median 25 d
- Micron Technology · 4 open roles · median 148 d
- NVIDIA · 4 open roles · median 60 d
- GlobalFoundries · 3 open roles · median 28 d
How we counted: 43 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 20 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.