Silicon Diagnosis DFT Engineer - CA, San Jose, United States
Originally posted 22 October 2026 by the employer.
Focus on scan DFT techniques, ATPG pattern validation, and electrical/physical fault isolation.
About the role
This role focuses on silicon debug and diagnosis capabilities, implementing features to meet diagnosis challenges using scan DFT knowledge. In the role of a PMTS, you will conduct electrical and physical fault isolation by generating diagnosis patterns and collaborating with design, verification, test engineering, and yield analysis groups.
What you'll do
- Perform post-silicon electrical and physical fault isolation. - Work with verification and test teams to make diagnosable tests. - Build layout databases for diagnosis and cross-probing. - Generate scan diagnosis tests for fault isolation and automate volume diagnosis and data analysis. - Develop and apply diagnosis patterns for Soft-Defect-Location or Laser-Voltage-Imaging. - Work with design and DFX teams for diagnosable designs.
What you'll need
- Degree in Electrical Engineering with knowledge of IC design, verification, or DFT (RTL, circuit, physical), and semiconductor physics. - Proficiency in IC design, automation, silicon product validation, characterization, or debug/diagnosis, particularly using scan DFT techniques. - Experience using commercial tools for ATPG and pattern validations.
Nice to have
- Familiarity with C/C++ or Verilog. - Scripting capability in Perl, Python, or TCL. - Experience in IC process technology, ATE, yield analysis, memory design, layout design, FPGA design tools (Xilinx Vivado), or validation tools (VCS, Caliber, Primetime).
This role has been open 0 days — well below the 61-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
61 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 248 |
| Open roles in the wider Digital Design & Verification family | 254 | 3298 · 115 employers |
| Median days open | 43 d | 61 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Who's hiring in this category
- AMD (this employer) · 39 open roles · median 43 d
- NVIDIA · 24 open roles · median 31 d
- Qualcomm · 23 open roles · median 105 d
- NXP Semiconductors · 19 open roles · median 45 d
- Synopsys · 15 open roles · median 28 d
- Intel Corporation · 10 open roles · median 62 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.