Silicon Design Engineer - San Jose, California, United States
Originally posted 19 March 2026 by the employer.
About the role
As a Silicon Design Engineer, you will be responsible for delivering RTL drops to physical design partners for AI silicon.
What you'll do
- Own RTL-to-PD handoff flows, including synthesis, timing constraints, UPF, and static checks to meet PPA targets. - Lead unit-level design execution and verification planning, collaborating across architecture, software, and design teams to develop MAS and test plans. - Drive timing closure by authoring timing constraints from RTL, executing static timing analysis, and resolving setup violations across multi-corner environments. - Execute floorplanning and physical implementation using Cadence or Synopsys tools to optimize macro placement and PPA. - Build and maintain scripted automated design flows for synthesis, analysis, and sign-off processes. - Contribute to post-DV design tasks including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline. - 3+ years of hands-on RTL-to-PD implementation experience taking designs from synthesis through tapeout. - Experience with MAS and test plan development, test implementation, and debugging across IP blocks, SoCs, and system-level designs. - Proficiency in SystemVerilog/Verilog, verification methodology, and C/C++ embedded code for processor validation. - Deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains. - Strong command of static timing analysis and the ability to author timing constraints from scratch based on RTL understanding.
This role has been open 119 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1070
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | persimmons | All employers we track in this specialty (1070 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1070 |
| Open roles in the wider Digital Design & Verification family | 2 | 3298 · 115 employers |
| Median days open | 119 d | 62 d (+57 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 153 open roles · median 58 d
- Synopsys · 87 open roles · median 35 d
- AMD · 76 open roles · median 40 d
- Analog Devices · 49 open roles · median 51 d
- NXP Semiconductors · 42 open roles · median 90 d
- NVIDIA · 41 open roles · median 62 d
How we counted: 1070 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.