Silicon Design Engineer - CA, San Jose, United States
$120,000 - $182,000 USD yearly
Originally posted 29 April 2026 by the employer. Relisted by the employer on 30 July 2026.
About the role
You will lead and contribute to the design, integration, verification, and characterization of silicon testchips supporting FPGA and ASIC products.
What you'll do
- Drive timing-aware and physical-aware synthesis using tools such as Design Compiler to generate netlists. - Execute the digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout, including floorplanning, power planning, placement, CTS, routing, timing closure, signal integrity, and physical verification. - Close SoC timing with Static Timing Analysis (STA) using tools such as PrimeTime across PVT corners. - Drive tapeout readiness by performing physical signoff analyses including IR drop, electromigration (EM), noise, DRC/LVS verification, and cross-functional reviews. - Develop verification plans and testbenches to validate chip functionality, and generate test patterns for post-silicon validation. - Assist with post-silicon bring-up, debugging, and lab-based validation activities.
What you'll need
- Experience across RTL-to-GDS implementation, design verification, and post-silicon validation. - Experience with timing-aware/physical-aware synthesis and physical signoff (STA, IR drop, EM, DRC/LVS). - Bachelor's degree in electrical & electronics engineering or physical sciences with relevant industry experience.
Nice to have
- Advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences. - Understanding of CMOS circuit design fundamentals, semiconductor device physics, signal integrity, power integrity, and device reliability mechanisms. - Experience delivering silicon across advanced process technologies, including FinFET (7nm/5nm/3nm) and Gate-All-Around (GAA) nodes. - Expertise with implementation tools including Cadence Genus/Innovus and Synopsys Fusion Compiler. - Experience with silicon bring-up, post-silicon validation, and laboratory test equipment. - Proficiency in Python, Tcl, and shell scripting.
Skills: micro-architecture, Verilog/SystemVerilog, synthesis, Static Timing Analysis, post-silicon bring-up
This role has been open 177 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1083
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1083 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 77 | 1083 |
| Open roles in the wider Digital Design & Verification family | 251 | 3328 · 115 employers |
| Median days open | 42 d | 64 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: micro-architecture, Verilog/SystemVerilog, synthesis, Static Timing Analysis, post-silicon bring-up
Who's hiring in this category
- Qualcomm · 160 open roles · median 61 d
- Synopsys · 87 open roles · median 37 d
- AMD (this employer) · 77 open roles · median 43 d
- Analog Devices · 49 open roles · median 54 d
- NXP Semiconductors · 42 open roles · median 93 d
- NVIDIA · 40 open roles · median 64 d
How we counted: 1083 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.