Silicon Design Architect
Originally posted 22 September 2026 by the employer.
About the role
This role defines the architecture and technical direction for complex semiconductor IPs and subsystems at Astera Labs, focusing on connectivity solutions that integrate CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies.
What you'll do
- Define architecture for complex IP blocks and SoC subsystems based on product and system requirements.
- Translate system requirements into architecture, specifications, interfaces, and performance targets.
- Define microarchitecture, data paths, control paths, interfaces, clocking, reset, power, and error-handling mechanisms.
- Evaluate architectural trade-offs across performance, power, area, latency, bandwidth, scalability, and complexity.
- Define interfaces and protocols such as PCIe, UALink, AXI, APB, CHI, or other high-speed/interconnect protocols.
- Develop architecture specifications, block diagrams, interface specifications, and technical documentation.
What you'll need
- Strong background in IP architecture and microarchitecture.
- Strong understanding of digital design, computer architecture, memory systems, interconnects, and SoC design.
- Experience with high-speed interfaces and/or coherent interconnects.
- Strong understanding of performance modeling, bandwidth, latency, and system-level trade-offs.
Nice to have
- Experience with PCIe, UALink, CXL, Ethernet, CCIX, CHI, or similar technologies.
- Experience with AI/accelerator, networking, compute, or high-performance SoC architectures.
- Experience taking IP/subsystems from architecture through silicon production.
Skills: IP architecture, SoC subsystems, microarchitecture, performance modeling, high-speed interfaces, PCIe
More semiconductor jobs: Astera Labs jobs · SoC design jobs · India jobs
This role has been open 44 days — well below the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
492
|
Median days open
77 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (492 roles · 68 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 492 |
| Open roles in the wider Digital Design & Verification family | 66 | 3497 · 120 employers |
| Median days open | 123 d | 77 d (+46 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: IP architecture, SoC subsystems, microarchitecture, performance modeling, high-speed interfaces, PCIe
Who's hiring in this category
- Qualcomm · 79 open roles · median 90 d
- NVIDIA · 63 open roles · median 78 d
- Apple · 39 open roles · median 16 d
- AMD · 37 open roles · median 71 d
- Arm Holdings · 28 open roles · median 8 d
- Micron Technology · 20 open roles · median 89 d
How we counted: 492 open SoC/Chip Architecture (SOC Architecture) roles from 68 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.