Signal Integrity Senior Engineer - US - Headquarters, United States
$159,000 - $170,000 USD yearly
Originally posted 22 June 2026 by the employer — open 80 days.
About the role
This role involves leading Signal Integrity and Power Integrity analysis for complex PCB and system designs within Upscale AI.
What you'll do
- Lead Signal Integrity and Power Integrity analysis for complex PCB and system designs.
- Define SI/PI architecture, design rules, and channel budgets for high-speed interfaces.
- Perform detailed channel simulations and optimization using industry-standard tools.
- Drive correlation between simulation and laboratory measurements.
- Develop and validate models for packages, PCBs, connectors, cables, and complete channels.
- Debug complex signal integrity issues and drive root-cause resolution.
What you'll need
- BS/MS in Electrical Engineering or related field.
- 5+ years of experience in Signal Integrity, High-Speed Design, or related areas.
- Strong understanding of Signal Integrity, Power Integrity principles, Electromagnetic theory, Transmission line analysis, high-speed SerDes architectures, PCB and package design, and Channel compliance methodologies.
- Extensive hands-on experience with Ansys HFSS, Cadence Clarity, Cadence Sigrity, and Keysight ADS.
- Strong laboratory experience with Vector Network Analyzer (VNA), TDR/TDT systems, high-bandwidth oscilloscopes, de-embedding and calibration techniques.
- Experience analyzing PCB channels, Connectors, Cables, Packages, Backplanes, and midplanes, and ability to correlate simulations with measured results and drive design improvements.
Nice to have
- Experience with 112G/224G PAM4 SerDes systems.
- Experience with Ethernet, PCIe, UCIe, CXL, DDR, or AI networking products.
- Knowledge of COM, ERL, eye analysis, jitter decomposition, and channel compliance methodologies.
- Experience with Python, MATLAB, or automation frameworks.
- Experience leading SI strategy for large-scale hardware programs.
Skills: Signal Integrity, Power Integrity, high-speed interfaces, SerDes architectures, channel simulations
This role has been open 45 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Upscale AI | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 1 | 1317 · 100 employers |
| Median days open | 45 d | 91 d (−46 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Signal Integrity, Power Integrity, high-speed interfaces, SerDes architectures, channel simulations
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.