Signal Integrity & Power Integrity Engineer - Mountain View, CA, United States
$215,000 - $275,000 USD yearly
Originally posted 2 July 2026 by the employer.
Own the signal-integrity and power-integrity engineering for our AI accelerator.
About the role
Own the signal-integrity and power-integrity engineering that keeps our AI accelerator running clean across die, package, and board. You will model and sign off the high-speed interface channels and power-delivery networks that move data and power through the system.
What you'll do
- Own signal-integrity and power-integrity analysis and signoff for DensityAI’s AI platform across silicon, package, board, and system. - Own high-speed interface channels, power delivery, and decoupling strategy.
What you'll need
- Exceptional abilities across SI/PI analysis: link budgeting, channel modeling, S-parameter extraction, IBIS-AMI, IR-drop and power-delivery-network (PDN) analysis, and EM/thermal-aware signoff. - 5+ years of SI/PI experience on very high-performance designs at advanced technology nodes (7nm or better) and high-speed interfaces (PCIe, DDR/LPDDR, HBM, 112G+ SerDes, or equivalent). - Hands-on experience with industry-standard tools (Ansys HFSS / SIwave / RedHawk, Cadence Sigrity / Clarity, Synopsys, Keysight ADS or equivalent) for extraction, EM, and PDN analysis. - Demonstrated ability to work closely with package, PCB, physical design, and architecture teams to set and sign off SI/PI budgets across die–package–board.
Nice to have
- 2.5D / 3D and multi-die packaging (CoWoS, EMIB, chiplets, HBM interfaces), jitter / equalization design, co-packaged optics, or post-silicon SI/PI correlation and lab validation.
Skills: signal integrity, power integrity, high-speed interface, PDN analysis, IBIS-AMI, 2.5D/3D packaging
This role has been open 34 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
78 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | DensityAI | All employers we track in this specialty (241 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 1 | 1412 · 104 employers |
| Median days open | 34 d | 78 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: signal integrity, power integrity, high-speed interface, PDN analysis, IBIS-AMI, 2.5D/3D packaging
Who's hiring in this category
- Synopsys · 31 open roles · median 30 d
- AMD · 30 open roles · median 39 d
- Cadence Design Systems · 19 open roles · median 188 d
- Qualcomm · 19 open roles · median 57 d
- Micron Technology · 14 open roles · median 53 d
- Apple · 12 open roles · median 16 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.