Signal Integrity Intern, MS – 2027 Co-Op - CA-ON - Toronto - TOR, Canada
$30 - $41 USD yearly
Originally posted 28 September 2026 by the employer.
About the role
This role involves establishing and maintaining interconnect Signal Integrity (SI) and Power Integrity (PI) design rules for Marvell's AMS IPs.
What you'll do
- Develop Python or similar scripting tools to automate SI/PI simulation workflows.
- Build and maintain automated trace/via design rule models for floorplan, Redistribution Layer (RDL), bump patterns, interposer, and package routing.
- Perform 2D/3D electromagnetic (EM) modeling and simulation using tools such as Ansys 3D Layout or Cadence Sigrity.
- Post-process SI/PI simulation results to extract key metrics and generate summary reports.
What you'll need
- Currently pursuing a master’s degree in electrical engineering, Electromagnetics, or a related field with an expected graduation date between Fall 2027 – Summer 2028.
- Basic background of Signal Integrity fundamentals, including transmission line theory, electromagnetic (EM), and microwave theory.
- Understand analog circuit and digital circuit basics.
- Proficiency in scripting languages such as Python or MATLAB for automation and data processing.
Nice to have
- Experience with SPICE simulation tools for circuit-level signal and power integrity analysis.
Skills: signal integrity, power integrity, high-speed interconnects, EM modeling, RDL design
This role has been open 1 day — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 20 | 1385 · 108 employers |
| Median days open | 185 d | 76 d (+109 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: signal integrity, power integrity, high-speed interconnects, EM modeling, RDL design
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.