Signal Integrity Engineer - Austin, Texas, United States
$100,000 - $500,000 USD yearly
Originally posted 27 March 2026 by the employer — open 167 days.
About the role
This role involves designing and verifying high-speed interconnects, including breakout design, material trade-offs, and verification.
What you'll do
- Design, extract, and simulate complex breakout structures, including end-to-end simulations and validation against physical hardware.
- Perform simulation and extraction of board models for both SI and PI.
- Contribute to design and sign-off with internal and external ASIC packaging teams, ODMs, and internal layout teams.
- Create design specifications, work with external vendors, and drive adoption of new interconnect and packaging technologies.
- Actively participate in design reviews, providing insight from SI/PI expertise and a broader system perspective.
- Support post-silicon bring-up and troubleshoot production and field failures related to signal and power integrity.
What you'll need
- Bachelor’s degree in Electrical Engineering (or equivalent) and 5+ years working in high-speed digital design with a focus in high-speed PCB or package design at 10Gbps and above.
- Experience with high-speed performance metrics such as ICR, ERL, COM, NEXT, and FEXT.
- Knowledge of high-speed connector technologies, including NPO, CPO, and emerging standards.
- Proficiency with PCB ECAD tools (ideally Cadence Allegro).
Skills: signal integrity, high speed interconnects, high-speed PCB design, package design, ICR, ERL, COM, NEXT, FEXT, Cadence Allegro
This role has been open 166 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tenstorrent | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 4 | 1317 · 100 employers |
| Median days open | 180 d | 91 d (+89 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: signal integrity, high speed interconnects, high-speed PCB design, package design, ICR, ERL, COM, NEXT, FEXT, Cadence Allegro
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.