Signal Integrity Engineer - Mountain View, CA, United States
$157,000 - $176,000 USD yearly
Originally posted 19 August 2026 by the employer — open 21 days.
About the role
What you'll do
- Plan and execute signal integrity engineering tasks for high-speed interfaces such as PCIe, UCIe, and SerDes.
- Analyze high-speed channel characteristics including S-parameters, insertion loss, return loss, and crosstalk.
- Perform signal integrity analysis and simulations including eye diagram analysis, jitter analysis, and equalization.
- Collaborate with hardware designers and PCB layout engineers on individual and team projects.
- Assist hardware designers in ensuring proper impedance matching, termination, and routing techniques.
- Perform detailed signal integrity measurements and characterization using lab equipment (oscilloscopes, network analyzers, TDRs, VNA).
What you'll need
- B.S. or M.S. degree in Electrical Engineering or relevant field with a minimum of 5 years of related experience.
- Professional knowledge in signal integrity analysis for high-speed interfaces.
- Proficiency in using simulation and analysis tools for signal integrity, including Ansys Siwave, HFSS, and Keysight ADS.
- Understanding of transmission line theory, impedance matching, and equalization techniques.
- Knowledge of signaling protocols for high-speed interfaces, including SerDes, UCIE.
- Experience with PCB design and layout considerations for high-speed interfaces (layer stack-up, routing, and via design).
- Proficiency in using lab equipment for signal measurement and characterization.
- Ability to write scripts to automate the simulation flow (Python, JavaScript, Ocean scripts, or SKILL).
Nice to have
- Problem-solving and debugging skills for signal integrity-related issues.
- Understanding of CMOS process technologies and their impact on signal integrity.
Skills: Signal Integrity, PCIe, UCIe, SerDes, S-parameters, jitter analysis
This role has been open 21 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lightmatter | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 6 | 1317 · 100 employers |
| Median days open | 100 d | 91 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Signal Integrity, PCIe, UCIe, SerDes, S-parameters, jitter analysis
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.