Signal Integrity Engineer - USA-CA San Jose Innovation Drive, United States
Analog & Mixed-Signal Design
$143,800 USD yearly
Originally posted 9 June 2026 by the employer — open 92 days. Relisted by the employer on 25 August 2026.
About the role
What you'll do
- Perform mask based timing signoff using time domain simulations (SPICE, etc.) of parallel interfaces including 2.5D and 3D.
- Conduct electromagnetic extraction and modeling of signal and power delivery channels (PCB, Package, Interposers, etc.).
- Perform AC and transient analysis of Power Distribution Networks.
- Conduct IO channel analysis.
- Perform pre-layout modeling of transceivers as well as signal and PDN networks.
- Automate sign-off processes and collaborate with EDA suppliers to improve tool accuracy and analysis flow.
What you'll need
- Knowledge of at least one DDR/LPDDR and/or HBM SI/PI sign-off flow tool suite.
- Experience with various IC, Package and PCB database types.
- TCL, Python scripting experience to automate routine tasks.
- Bachelors and 12+ years of related experience; or Masters degree and 10+ years of related experience.
Nice to have
- Independent, self-starter who can work across a worldwide organization and customer base.
- Ability to manage multiple concurrent customers under short timelines.
- Comfortable with providing guidance and direction with incomplete information.
- Ability to manage analysis, documentation, and presentation roles.
- Flexibility to integrate new ideas and tools to enhance signoff capabilities.
Skills: SI/PI, parallel interfaces, 2.5D, 3D interconnects, SPICE, Power Distribution Networks
Market context
This role has been open 164 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 11 | 217 |
| Median days open | 142 d | 91 d (+51 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SI/PI, parallel interfaces, 2.5D, 3D interconnects, SPICE, Power Distribution Networks
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom (this employer) · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.