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Graphcore

Signal Integrity Engineer - Bristol, United Kingdom

Graphcore Remote friendly (Bristol, United Kingdom) 2 months ago
Analog & Mixed-Signal Design

Originally posted 22 July 2026 by the employer.

About the role

This role involves designing high-speed signal paths for advanced AI compute systems.

What you'll do

  • Develop, extract, and simulate PCB structures across production systems and test boards.
  • Define launches, via structures, transmission lines, stack-ups, and low-loss materials.
  • Engage in simulation, lab validation, and practical design influence from concept through debug and validation.
  • Own signal integrity decisions across complex board and package interfaces.
  • Challenge designs, guide constraints, and help teams achieve optimal performance.

What you'll need

  • Strong experience in high-speed digital circuit development with deep signal and power integrity knowledge.
  • Experience with high-frequency SERDES design and validation, including tens of GHz operation.
  • Expertise using tools such as ANSYS SIWave, HFSS, Mentor HyperLynx or similar.
  • Ability to design BGA and connector launches, via structures, and transmission lines for GHz signals.
  • Hands-on lab experience using VNAs, high-speed oscilloscopes, and signal generators.
  • Rigorous approach to design, debug, and validation.

Skills: Signal Integrity, high-speed SERDES, 112Gbps/224Gbps, DDR interfaces, ANSYS SIWave, HFSS

Market context

This role has been open 69 days — below the 78-day median for High-Speed IO/SerDes Design roles.

High-Speed IO/SerDes Design · Serdes Highspeed

Open roles in category
238
Median days open
78 d
Median salary
$177k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Graphcore compares in High-Speed IO/SerDes Design hiring
Metric Graphcore All employers we track in this specialty (238 roles · 49 employers)
Open roles in this specialty 3 238
Open roles in the wider Analog & Mixed-Signal family 6 1385 · 107 employers
Median days open 69 d 78 d (−9 d vs this employer)
Median salary (USD postings) — $177k

Skills observed across this category: Signal Integrity, high-speed SERDES, 112Gbps/224Gbps, DDR interfaces, ANSYS SIWave, HFSS

Who's hiring in this category

  • AMD · 27 open roles · median 66 d
  • Synopsys · 25 open roles · median 46 d
  • Qualcomm · 20 open roles · median 57 d
  • Cadence Design Systems · 18 open roles · median 180 d
  • Micron Technology · 11 open roles · median 75 d
  • Apple · 10 open roles · median 12 d

How we counted: 238 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.

Graphcore

Graphcore

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Bristol, United Kingdom
Hybrid
2 months ago

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