Signal and Power Integrity Intern, MS - Summer 2027 - Santa Clara, CA, United States
Originally posted 26 October 2026 by the employer.
About the role
This on-site role in Santa Clara focuses on advanced packaging design covering SI/PI and physical designs. The team is responsible for packaging design for photonic fabric products, including CPO and NPO platforms.
What you'll do
- Define a template modeling and simulation flow to automate channel and packaging analysis. - Apply the template to automate the modeling process across various field solvers. - Build an automation flow to link various package models directly to simulation decks.
What you'll need
- Currently enrolled in a Bachelor's or Master's degree in Electrical Engineering or related field with an expected graduation date between Fall 2027 – Summer 2028. - Prior coursework in electronics, circuit design, and programming, alongside knowledge of circuit design and analysis. - Understanding of chip physical integration and layout concepts. - Skills in circuit simulation tools such as SPICE and Matlab. - Familiarity with Cadence Allegro, Ansys HFSS, Siwave, and Sigrity. - Understanding of IBIS and S-parameter models, with familiarity using Python for automation or scripting.
Skills: Signal Integrity, Power Integrity, HFSS, Siwave, Sigrity, SPICE
This role has been open 0 days — well below the 73-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
244
|
Median days open
73 d
|
Median salary
$191k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (244 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 244 |
| Open roles in the wider Analog & Mixed-Signal family | 29 | 1453 · 106 employers |
| Median days open | 27 d | 73 d (−46 d vs this employer) |
| Median salary (USD postings) | — | $191k |
Skills observed across this category: Signal Integrity, Power Integrity, HFSS, Siwave, Sigrity, SPICE
Who's hiring in this category
- Synopsys · 35 open roles · median 38 d
- AMD · 27 open roles · median 44 d
- Cadence Design Systems · 21 open roles · median 139 d
- Qualcomm · 21 open roles · median 68 d
- Micron Technology · 14 open roles · median 41 d
- Apple · 9 open roles · median 27 d
How we counted: 244 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.