Signal and Power Integrity Engineer, Senior to Staff Level - Hsinchu City, Taiwan
Originally posted 14 August 2026 by the employer — open 27 days.
About the role
You will work on various IPs such as LPDDR6, PCIe, and 224G interfaces.
What you'll do
- Perform package and PCB extraction for time-domain and frequency-domain analysis.
- Conduct system-level analysis for DDR, SerDes, and Power Delivery Network (PDN).
- Develop design guidelines for Package and PCB design.
- Create technical documentation and presentations.
- Collaborate with cross-functional teams to optimize signal and power integrity performance.
What you'll need
- 3 years of experience in DDR/SerDes, Package, PCB, or System Design related to Compute, Automotive, and/or Server products.
- Strong background in Electromagnetics, transmission line theory, and crosstalk analysis.
- Experience with field solvers such as HFSS, Q3D, Sentinel-PSI, and Clarity.
- Experience with simulation tools such as ADS and HSPICE.
- Working knowledge of Cadence Allegro/APD/SIP or Mentor Xpedition.
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ years of System/Package Design/Technology Engineering or related work experience OR Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 3+ years of System/Package Design/Technology Engineering or related work experience OR PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 2+ year of System/Package Design/Technology Engineering or related work experience.
Nice to have
- Experience utilizing AI tools to improve engineering efficiency.
- Experience with MATLAB and/or programming languages.
- Knowledge of design specifications such as LPDDRx, PCIe, and XLink.
- Master's degree or Ph.D. in Electrical Engineering or a related field.
Skills: DDR/SerDes, Package and PCB extraction, time-domain and frequency-domain analysis, Power Delivery Network (PDN), Electromagnetics, transmission line theory
This role has been open 27 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 76 | 1317 · 100 employers |
| Median days open | 75 d | 91 d (−16 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: DDR/SerDes, Package and PCB extraction, time-domain and frequency-domain analysis, Power Delivery Network (PDN), Electromagnetics, transmission line theory
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm (this employer) · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.