Signal and Power Integrity Engineer
Originally posted July 25, 2026 by the employer.
About the role
Volantis Semiconductor is hiring a Signal and Power Integrity Engineer to ensure power delivery network stability across rack/tray, package, die, and core levels.
What you'll do
- Analyze and design chip power delivery networks (PDN) for large die, high TDP architectures.
- Perform chip PDN analysis and design on advanced nodes (7nm and lower).
- Partner with package architects to determine optimal passives design within defined constraints.
- Work with ASIC and microarchitecture teams to meet power integrity goals within manufacturing design constraints.
What you'll need
- Experience with large die, high TDP chip PDN analysis and design.
- Experience with advanced node (7nm and lower) chip PDN analysis and design.
- Demonstrated ability to collaborate with package architects on passives design under constraints.
- Demonstrated ability to collaborate with ASIC and microarchitecture teams to meet power integrity targets.
Nice to have
- Experience with WSI (wafer-scale integration) systems.
- Board and system-level power delivery network analysis and design.
- Low voltage die power delivery network analysis and design.
- Many voltage domain power delivery network design and analysis.
- IVR based design experience.
Skills: power integrity, signal integrity, PDN, package, TDP
More semiconductor jobs: Signal integrity jobs
First seen in our index 0 days ago, well below the 58-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
262
|
Median days since first seen
58 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Volantis Semiconductor | All employers we track in this specialty (262 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 262 |
| Open roles in the wider Analog & Mixed-Signal family | 3 | 1598 · 127 employers |
| Median days since first seen | 0 d | 58 d (+58 d vs this employer) |
| Median salary (USD postings) | n/a | $206k |
Skills observed across this category: power integrity, signal integrity, PDN, package, TDP
Who's hiring in this category
- Synopsys · 41 open roles · median 37 d
- Cadence Design Systems · 22 open roles · median 150 d
- AMD · 21 open roles · median 46 d
- Qualcomm · 20 open roles · median 87 d
- NVIDIA · 18 open roles · median 219 d
- Apple · 10 open roles · median 13 d
How we counted: 262 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 53 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Analog & Mixed-Signal family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.