SiC Wafer & Package Technology Development Engineer - Hsinchu City, Taiwan
Originally posted 29 September 2026 by the employer.
About the role
This role involves technical and customer support for the qualification of SiC die sales and development, focusing on package design, assembly processes, and device interactions.
What you'll do
- Develop and qualify SiC technologies to meet cost, performance, manufacturing, timeline, and reliability goals.
- Lead development projects and implement strategies on a global basis.
- Document findings and process flows to create baselines for new technology platforms.
- Lead maturity gate reviews and publish progress reports to executives and peers.
- Update customer assembly application notes.
What you'll need
- MS Degree in Material Science, Chemical Engineering, Semiconductor Processes or relevant technical field.
- Knowledge of package design, assembly processes, and device interactions.
- Knowledge of post fab processing such as wafer thinning, sputter, electroplating, electroless plating, photolithography, wafer bonding.
- Knowledge of wafer level packaging, package assembly, and component processes like wirebond, sintering, die attach, clip attach, reflow, molding.
- Knowledge of materials and material interactions.
- Strong English conversational skills.
Skills: SiC Wafer, Package Technology Development, wafer thinning, electroplating, wafer level packaging, die attach
This role has been open 1 day — well below the 74-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
202
|
Median days open
74 d
|
Median salary
$165k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (202 roles · 42 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 202 |
| Open roles in the wider Process, Fab & Equipment family | 283 | 9593 · 108 employers |
| Median days open | 17 d | 74 d (−57 d vs this employer) |
| Median salary (USD postings) | — | $165k |
Skills observed across this category: SiC Wafer, Package Technology Development, wafer thinning, electroplating, wafer level packaging, die attach
Who's hiring in this category
- Infineon Technologies · 27 open roles · median 41 d
- Renesas Electronics · 23 open roles · median 33 d
- Micron Technology · 17 open roles · median 147 d
- Intel Corporation · 12 open roles · median 158 d
- Monolithic Power Systems · 12 open roles · median 194 d
- onsemi (this employer) · 12 open roles · median 17 d
How we counted: 202 open Packaging Engineering (Packaging) roles from 42 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.