Server Power Management Sr. Staff Architect - San Diego, California, United States of America
$198,700 - $298,100 USD yearly
Originally posted 9 July 2026 by the employer — open 73 days.
About the role
This role involves defining the architecture of the end-to-end power management of a Server SoC. The focus is on developing server-class high performance solutions that are highly optimized for the needs of the server product.
What you'll do
- Work with chip architects to understand architecture concept and high level system requirements
- Collaborate with HW, SW, and FW architects to develop an optimal end-to-end power management architecture
- Execute System level power modeling for server use cases and analyze trade-offs
- Drive convergence of SoC and board power grid definition
- Architect SoC and system level power rail sequencing
- Create detailed architecture specification documents
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- Deep understanding of Server SoC designs
- Extensive knowledge of CPU and SoC power management architecture for datacenter SoCs
- Experience in microarchitecture and design of power management components for a modern SoC
- Strong analytical skills
- Strong problem-solving skills
Nice to have
- Over 10 years of experience in power management of CPU and/or SoCs
- At least 5 years of experience with a high-performance server chip
- Expertise in power management of a high-performance system including management of active power, idle low power and silicon/system limits
- Experience in power delivery systems including multi-phase bucks and LDOs
- Fundamentals in digital ASIC design and power of CMOS circuits
- Experience in TDP (thermal design power) capping and control
- Experience in measurement and management of over-current and voltage droop events
- Experience in developing solutions for power and performance telemetry
- Understanding of silicon test methodologies for power and thermal optimization
- Experience in designing SoCs for systems using off-the-shelf PMICs
- Track record in hyperscale data center solutions
- Familiarity with high performance and low power design techniques
Skills: power management architecture, SoC power, power delivery systems, TDP, thermal optimization
This role has been open 72 days — slightly above the 71-day median for Power Electronics roles.
Power Electronics · Power Management
|
Open roles in category
71
|
Median days open
71 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (71 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 71 |
| Open roles in the wider Analog & Mixed-Signal family | 73 | 1337 · 105 employers |
| Median days open | 39 d | 71 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Skills observed across this category: power management architecture, SoC power, power delivery systems, TDP, thermal optimization
Who's hiring in this category
- Renesas Electronics · 15 open roles · median 75 d
- Qualcomm (this employer) · 8 open roles · median 38 d
- Analog Devices · 6 open roles · median 81 d
- Monolithic Power Systems · 6 open roles · median 184 d
- AMD · 5 open roles · median 89 d
- Infineon Technologies · 5 open roles · median 72 d
How we counted: 71 open Power Electronics (Power Management) roles from 25 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.