Server IO Specialist. Sr. Director of Technology - Santa Clara, California, United States of America
$284,900 - $427,300 USD yearly
Originally posted 9 July 2026 by the employer.
Architecture through commercialization of server IO solutions spanning PCIe, CXL, and UAL.
About the role
This role involves architecture through commercialization of the end-to-end Server IO solution, spanning PCIe and CXL technologies as well as emerging technologies like UAL. The position focuses on datacenter SoCs, covering microarchitecture, coherent IO subsystems, and horizontal SoC technologies including coherency, power management, debug, and RAS.
What you'll do
- Work with chip architects to understand architecture concepts and high-level requirements.
- Define and document IO architecture requirements and solutions for the chip.
- Collaborate with IP design and performance teams to optimize the end-to-end solution for PPA trade-offs.
- Evangelize and communicate architectural definitions to silicon, system, and software stakeholders.
- Participate in new product development, comprehend customer technical requirements, and develop architectural solutions to meet those requirements.
- Work with design and verification teams to ensure implementation matches specification.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 10+ years of hardware, software, electrical, or systems engineering experience (or Master's degree with 9+ years, or PhD with 8+ years).
- Experience in hardware engineering, software engineering, systems engineering, or related technical disciplines.
- Technical experience in CPU or SoC architecture for datacenter SoCs, including coherent IO subsystems.
Nice to have
- Over 15 years of experience in architecting solutions for PCIe, CXL, or similar IO technologies.
- Strong expertise in IOMMU / SMMU architecture and micro-architecture.
- In-depth understanding of fully coherent and IO coherent protocol flows.
- 12 years in developing IO architecture for high-speed IO like PCIe Gen5-7, CXL2.0-CXL3.0.
- Expertise in performance microarchitecture of IO datapath between host and devices.
- Expertise in architecture and application of confidential compute technologies like TDISP, IDE, and TSP for IO interfaces.
- Experience in architecture and development of multi-socket links like UPI, C2C, or Infinity fabrics.
- End-to-end experience with the IO hardware stack from TL (Transport Layer) to PL (Physical Layer).
- Experience with ARM ISA and related specifications like SMMU, CHI, and GIC.
- Familiarity with accelerator technologies like UAL and NVLink.
Skills: PCIe, CXL, IOMMU, coherent protocol, SoC architecture, microarchitecture
This role has been open 102 days — well above the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
475
|
Median days open
77 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (475 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 76 | 475 |
| Open roles in the wider Digital Design & Verification family | 398 | 3244 · 116 employers |
| Median days open | 87 d | 77 d (+10 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: PCIe, CXL, IOMMU, coherent protocol, SoC architecture, microarchitecture
Who's hiring in this category
- Qualcomm (this employer) · 76 open roles · median 87 d
- NVIDIA · 55 open roles · median 70 d
- Apple · 38 open roles · median 13 d
- AMD · 34 open roles · median 63 d
- Arm Holdings · 27 open roles · median 118 d
- Micron Technology · 22 open roles · median 110 d
How we counted: 475 open SoC/Chip Architecture (SOC Architecture) roles from 66 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.