SerDes IP Systems Engineering Director - San Jose, United States
$178,500 - $331,500 USD yearly
Originally posted 22 June 2026 by the employer.
About the role
As the SerDes IP Systems Engineering Director in the Silicon Solutions R&D Group, you will lead the D2D Systems analysis team and contribute hands-on technical development for D2D SerDes IP products. The scope includes statistical and linear systems link analysis, microarchitecture definition, and establishing design specifications for circuit designers.
What you'll do
- Develop statistical and linear systems analysis of the link, model nonidealities, and determine design specifications for circuit designers. - Define, model, and analyze high-performance D2D SerDes IP microarchitecture, link budget, and specifications. - Drive and verify end-to-end link simulations using statistical and time-domain simulators such as Simulink and ADS. - Develop and provide guidelines regarding signal integrity and power integrity to customers, while supporting package/board design and debug. - Guide the package design team based on in-package D2D link channel analysis. - Generate technical specifications, data sheets, and application notes while tracking standards developments and competitive analysis.
What you'll need
- 10+ years of experience working with high speed high performance SerDes and PHYs. - PhD or M.S. in Electrical/Computer Engineering (or similar degree). - Deep understanding of high speed SerDes architecture, communication systems fundamentals, and wireline communications. - Proficiency in MATLAB, Simulink, ADS, or similar link analysis/statistical analysis tools. - Strong coding skills for simulation, modeling, and data analysis using tools such as Matlab, Perl, and scripting languages. - Experience generating systems or IBIS-AMI models. - Deep knowledge of signal processing (DSP) algorithms, architecture, and linear systems mathematics such as Fourier analysis and filter theory.
Nice to have
- D2D link experience. - Familiarity with emerging D2D standards such as UCIe.
Skills: SerDes IP, D2D SerDes, signal integrity, power integrity, system modeling, wireline communications
This role has been open 215 days — well above the 71-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
247
|
Median days open
71 d
|
Median salary
$191k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (247 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 247 |
| Open roles in the wider Analog & Mixed-Signal family | 32 | 1453 · 106 employers |
| Median days open | 139 d | 71 d (+68 d vs this employer) |
| Median salary (USD postings) | — | $191k |
Skills observed across this category: SerDes IP, D2D SerDes, signal integrity, power integrity, system modeling, wireline communications
Who's hiring in this category
- Synopsys · 34 open roles · median 36 d
- AMD · 27 open roles · median 45 d
- Cadence Design Systems (this employer) · 21 open roles · median 140 d
- Qualcomm · 21 open roles · median 69 d
- Micron Technology · 13 open roles · median 41 d
- Apple · 12 open roles · median 25 d
How we counted: 247 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.