SerDes/DSP System, Sr Architect - 18614
Originally posted 3 September 2026 by the employer.
About the role
This role is for a Senior Architect to develop and maintain SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
What you'll do
- Develop and maintain SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
- Run comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.
- Design and propose advanced algorithms to calibrate and adapt transceivers for optimal performance.
- Correlate simulated performance with silicon measurements to ensure accuracy and reliability.
- Provide expert assistance to customers for system-level performance issues and troubleshooting.
- Contribute to lab testing and analysis for high-speed serial links, ensuring robust design validation.
What you'll need
- M.Sc. or Ph.D. in Electrical or Computer Engineering with 13+ years of relevant experience.
- Strong experience modeling circuits and systems in MATLAB/Simulink.
- Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering.
- Proficiency in analyzing link budgets for PAM4 high-speed serial links.
- Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
- Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
- Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/system Verilog.
Nice to have
- Programming in Python is a plus.
Skills: SerDes, PAM4, PCIe, Ethernet, DSP
This role has been open 30 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
78 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (241 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 45 | 1412 · 104 employers |
| Median days open | 30 d | 78 d (−48 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: SerDes, PAM4, PCIe, Ethernet, DSP
Who's hiring in this category
- Synopsys (this employer) · 31 open roles · median 30 d
- AMD · 30 open roles · median 39 d
- Cadence Design Systems · 19 open roles · median 188 d
- Qualcomm · 19 open roles · median 57 d
- Micron Technology · 14 open roles · median 53 d
- Apple · 12 open roles · median 16 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.