SerDes Circuit Design Engineer - Austin Metro Area, United States
Originally posted 26 October 2026 by the employer.
Design high-speed AMS circuits and wireline transceivers for Apple SOCs.
About the role
As a SerDes Circuit Design Engineer, you will develop high-performance and high-speed analog mixed-signal circuits used in SerDes PHY architectures for Apple system-on-chip (SOC) designs.
What you'll do
- Develop high-speed AMS circuits used in SerDes PHY designs, evaluating circuit topologies for Rx, CDR, Tx, bias generators, high-speed clock generation, low-jitter distribution, high-speed analog signal chains, and mixed-signal calibrations. - Collaborate with architecture, SIPI, packaging, board design, DFT, and ESD teams to create block-level specifications. - Execute transistor-level implementation and behavioral modeling to achieve power, performance, and area (PPA) targets. - Drive mask design to implement layout views and deliver verified IP views to SOC teams.
What you'll need
- Bachelor's degree in a relevant engineering discipline.
Nice to have
- Deep understanding of analog mixed-signal design with experience in high-speed serial links. - Experience designing circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, and Filters. - Knowledge of Tx/Rx equalization techniques and circuits (e.g., CTLE, DFE, de-emphasis) for 64+ Gbps NRZ and PAM applications, as well as CDR architectures. - Experience with AMS circuit modeling using SystemVerilog, Matlab, Python, or VerilogAMS. - Hands-on experience in advanced CMOS technologies, including FinFET design, through layout supervision, bench evaluation, correlation, and characterization. - Knowledge of high-speed SerDes protocols such as PCIe, USB, DP, and MPHY, along with timing closure tools like Nanotime and Primetime.
Skills: SerDes, CDR, CTLE, DFE, PAM, transistor-level implementation
This role has been open 0 days — well below the 73-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
244
|
Median days open
73 d
|
Median salary
$191k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (244 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 244 |
| Open roles in the wider Analog & Mixed-Signal family | 55 | 1453 · 106 employers |
| Median days open | 25 d | 73 d (−48 d vs this employer) |
| Median salary (USD postings) | — | $191k |
Skills observed across this category: SerDes, CDR, CTLE, DFE, PAM, transistor-level implementation
Who's hiring in this category
- Synopsys · 35 open roles · median 38 d
- AMD · 27 open roles · median 44 d
- Cadence Design Systems · 21 open roles · median 139 d
- Qualcomm · 21 open roles · median 68 d
- Micron Technology · 14 open roles · median 41 d
- Apple (this employer) · 9 open roles · median 27 d
How we counted: 244 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.