Senior Yield Enhancement Engineer #9573 - USA-Arizona, United States
Originally posted 16 March 2026 by the employer.
Transfer advanced semiconductor technology below N4 to drive yield enhancement and inline defect reduction.
About the role
Transfer advanced semiconductor technology (below N4 technology) to overseas fabs to drive product yield improvement and meet customer requirements. The scope centers on advanced processes including N4, N3, and N2 technologies.
What you'll do
- Define a defect reduction roadmap, identify potential yield-limiting defect sources, and collaborate across integration, process engineering, and manufacturing to optimize processes. - Serve as the metrology tool and recipe owner, setting up and optimizing inline inspection and review recipes to enhance inline defect detection capability. - Monitor and detect integrated and process tool shifts in a high-volume manufacturing fab using inspection and review tools. - Provide production line guidance and utilize statistical process control principles to sustain production line health and prevent defect-induced excursion events. - Coordinate with process engineers to eliminate defect sources, design and execute experiments, and extract actionable results from complex data sets. - Serve as the project owner coordinating overall yield improvement, defect reduction, quality enhancement, and new process technology qualification.
What you'll need
- Master’s degree (or foreign equivalent) in Electrical Engineering, Material Science, Physics, or a related field plus 2 years of experience in a process, equipment, or integration semiconductor engineering role. - 1 year of experience studying recipes in at least one defect inspection metrology: Bright Field (BF) inspection tool, Dark Field (DF) inspection tool, or Electron Beam Inspection (EBI) tool. - 1 year of experience in at least one defect review metrology: Scanning Electron Microscopy (SEM), Critical Dimension SEM (CD-SEM), or Transmission Electron Microscopy (TEM). - Experience working in an ISO 4 (Class 10) or lower cleanroom environment. - Experience in at least one of the following areas: semiconductor physics, CMOS device operation, or advanced semiconductor manufacturing. - Experience with at least 2 of the following processes, including tool structure and process mechanisms: LIT, ETC, WET, CVD, PVD, DIF, and CMP.
Skills: yield-limiting defect, defect reduction roadmap, metrology tool and recipe owner, inline inspection, statistical process control
This role has been open 163 days — well above the 57-day median for Yield Engineering roles.
Yield Engineering · Yield Engineering
|
Open roles in category
221
|
Median days open
57 d
|
Median salary
$130k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | TSMC Arizona | All employers we track in this specialty (221 roles · 37 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 221 |
| Median days open | 163 d | 57 d (+106 d vs this employer) |
| Median salary (USD postings) | — | $130k |
Skills observed across this category: yield-limiting defect, defect reduction roadmap, metrology tool and recipe owner, inline inspection, statistical process control
Who's hiring in this category
- Micron Technology · 113 open roles · median 60 d
- GlobalFoundries · 11 open roles · median 172 d
- Intel Corporation · 11 open roles · median 23 d
- STMicroelectronics · 9 open roles · median 39 d
- Skyworks · 8 open roles · median 58 d
- onsemi · 5 open roles · median 95 d
How we counted: 221 open Yield Engineering (Yield Engineering) roles from 37 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.