Senior Verification & Simulation Product Engineer - CA, San Jose, United States
Originally posted 5 August 2026 by the employer.
This role focuses on UVM, SystemVerilog, and HDL simulation within the Vivado design tools ecosystem.
About the role
As a Senior Engineer for AMD Vivado™ Design Tools, you will serve as the technical owner for verification methodology and simulation technologies, with a primary focus on UVM, SystemVerilog, HDL simulation, and technical product strategy. You will lead the evolution of Vivado's simulation ecosystem, helping customers develop, verify, and deploy complex FPGA and adaptive SoC designs.
What you'll do
- Shape the strategic roadmap for simulation, RTL encryption/security, and deployment. - Drive competitive differentiation by understanding the market landscape. - Define third-party partnership strategy, ensuring interoperability, certification, and commercial alignment. - Represent AMD in industry standards bodies for IP protection and encryption. - Serve as the primary technical resource for strategic sales opportunities. - Lead high-stakes customer escalations with executive-level communication and resolution ownership.
What you'll need
- Deep expertise in UVM, SystemVerilog, and modern simulation methodologies. - Deep expertise in digital design verification. - Experience owning or significantly influencing a product roadmap in EDA, semiconductor tools, or a related technical domain. - Hands-on experience applying AI agents and copilots to drive EDA tools, automate engineering workflows, or solve complex technical problems. - Bachelor’s, Master's, or PhD degree in Computer Science, Computer Engineering, Electrical Engineering, with related experiences in UVM.
Nice to have
- Familiarity with IP protection/encryption technology and the compliance landscape surrounding it. - Comfort with licensing models, enterprise software deployment, or platform engineering. - Proven ability to communicate complex technical concepts to diverse audiences.
Skills: UVM, SystemVerilog, HDL simulation, Vivado, IP protection
This role has been open 74 days — slightly above the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
672
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (672 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 672 |
| Open roles in the wider Physical Implementation family | 88 | 1441 · 110 employers |
| Median days open | 24 d | 73 d (−49 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: UVM, SystemVerilog, HDL simulation, Vivado, IP protection
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 170 d
- Synopsys · 63 open roles · median 36 d
- Micron Technology · 44 open roles · median 47 d
- Qualcomm · 36 open roles · median 75 d
- GlobalFoundries · 33 open roles · median 38 d
- Keysight Technologies · 32 open roles · median 72 d
How we counted: 672 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.