Senior Verification Engineer – High Speed Coherent Interconnect Hub - CA, Santa Clara, United States
$136,000 - $264,500 USD yearly
Originally posted 20 October 2026 by the employer.
Verify High Speed Coherent Interconnect Hub IP on the Tegra SoC IP Verification team using SystemVerilog and UVM.
About the role
As a Senior Verification Engineer on the Tegra SoC IP Verification team, you will work closely with architecture and design teams to verify complex High Speed Coherent Interconnect Hub IP. You will define verification strategies, build verification environments, drive functional and performance verification, and achieve coverage closure for design signoff.
What you'll do
- Develop and maintain verification infrastructure, including testbenches, BFMs, checkers, monitors, scoreboards, assertions, and constrained-random stimulus. - Define, review, and complete verification test plans for coherency protocol, ordering, error handling, performance, and other IP features. - Verify protocol compliance and interoperability across complex SoC and multi-chip interfaces. - Develop and execute performance test plans to validate bandwidth, latency, QoS, and performance requirements. - Drive functional and code coverage closure leading to verification signoff. - Debug complex RTL and verification issues alongside architecture and design teams, and collaborate with FPGA, emulation, software, and post-silicon teams.
What you'll need
- BS or MS in a related field or equivalent experience. - 3+ years of ASIC verification experience with complex IPs or SoC subsystems. - Strong background in SystemVerilog, UVM, constrained-random verification, and coverage-driven verification methodologies. - Experience developing verification environments, checkers, assertions, and functional coverage. - Strong debugging skills using industry-standard simulation and debug tools.
Skills: SystemVerilog, UVM, constrained-random, testbenches, coverage closure
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1220
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1220 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 84 | 1220 |
| Open roles in the wider Digital Design & Verification family | 230 | 3283 · 116 employers |
| Median days open | 62 d | 64 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: SystemVerilog, UVM, constrained-random, testbenches, coverage closure
Who's hiring in this category
- Qualcomm · 114 open roles · median 41 d
- AMD · 94 open roles · median 52 d
- NVIDIA (this employer) · 85 open roles · median 62 d
- Synopsys · 65 open roles · median 36 d
- SiFive · 55 open roles · median 78 d
- Cadence Design Systems · 50 open roles · median 120 d
How we counted: 1220 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.