Senior Verification Engineer - CA, Santa Clara, United States
$168,000 - $310,500 USD yearly
Originally posted 23 July 2026 by the employer.
About the role
As a Senior Verification Engineer on the Display Team, you will own testplan development, verification sign-off, and infrastructure for GPU and SoC display engines. The role focuses on verifying IPs across consumer, professional, automotive, and AI markets.
What you'll do
- Define verification scope, develop and drive functional and performance testplans, and build scalable UVM-based infrastructure. - Develop UVM testbenches and checkers, work with C/C++-based testbenches, and debug reference models and designs developed in HLS. - Track metrics and drive coverage closure. - Partner with architects to evaluate architectural solutions and develop silicon-proven designs. - Collaborate across global sites and work with external partners and customers to deploy verification flows, ensure consistent display IP behavior across diverse tool stacks, and debug complex integration issues.
What you'll need
- BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent experience). - 10+ years of relevant experience. - Hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++, including constrained-random stimulus, functional coverage, assertion-based verification, and C/C++-based testbenches. - Proficiency with EDA tools including VCS, Verdi/Debussy, and GDB, along with version control and code review practices. - Domain knowledge of display pipelines, including protocols (DisplayPort, HDMI, MIPI DSI/CSI), MMU interaction with ISO clients, and system low-power features (clock gating, power domains, retention, entry/exit sequences).
Skills: UVM, testplan development, verification sign-off, SystemVerilog, EDA tools
This role has been open 88 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1201
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1201 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 84 | 1201 |
| Open roles in the wider Digital Design & Verification family | 231 | 3224 · 116 employers |
| Median days open | 61 d | 66 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM, testplan development, verification sign-off, SystemVerilog, EDA tools
Who's hiring in this category
- Qualcomm · 110 open roles · median 40 d
- AMD · 95 open roles · median 52 d
- NVIDIA (this employer) · 84 open roles · median 60 d
- Synopsys · 64 open roles · median 34 d
- SiFive · 55 open roles · median 76 d
- Cadence Design Systems · 50 open roles · median 118 d
How we counted: 1201 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.