Senior Validation & SI Correlation Engineer - San Jose, California, United States

Originally posted 6 April 2026 by the employer.

Validate PCIe Gen5/6, DDR5, and 112G/224G Ethernet interfaces across SambaNova RDU and SambaRack systems.

About the role

As a Senior Validation & SI Correlation Engineer, you will own the technical bridge between simulation and silicon, ensuring that high-speed links, control buses, and power rails in AI server systems perform to specification. The role focuses on validating PCIe Gen5/6, DDR5, and 112G/224G Ethernet interfaces across RDU and SambaRack architectures.

What you'll do

- Drive correlation between pre- and post-layout SI simulations and physical lab measurements for PCIe Gen5/6, DDR5, and 112G/224G Ethernet using S-parameters, TDR, and eye diagram analysis. - Develop and refine EM models for PCB discontinuities, high-speed connectors, and vias using Ansys HFSS, Cadence Sigrity, or equivalent tools. - Investigate discrepancies resulting from manufacturing tolerances, material properties (Dk/Df), or de-embedding inaccuracies. - Lead system-level validation of housekeeping and control buses including I2C, SPI, eSPI, UART, and SMBus to guarantee protocol compliance and timing margins. - Validate power-on/off sequences, sideband signals, reset logic, and BMC interfaces, correlating VR control loop simulations with physical transient response and ripple measurements. - Author Hardware Validation Plans (HVP) and develop Python-based automation scripts to drive data collection from VNAs, BERTs, and oscilloscopes.

What you'll need

- 10+ years of experience in high-speed digital design or hardware validation within a data center, systems architecture, or server bring-up environment. - B.S. or M.S. in Electrical Engineering. - Expert-level proficiency in SI/EM tools including Ansys HFSS/SIwave, Cadence Sigrity/Allegro, or Keysight ADS. - Hands-on mastery of high-bandwidth real-time oscilloscopes, VNAs, and logic analyzers. - Deep knowledge of high-speed protocol physical layers (PCIe, IEEE 802.3), low-speed control buses (I2C, SPI), and expertise in PCIe Gen5/6 and 100G Ethernet. - Programming fluency in Python or equivalent scripting languages (Perl, Shell).

Nice to have

- M.S. or Ph.D. with an emphasis in Electromagnetics, Computer Architecture, or Power Electronics. - Hands-on experience validating GPU/TPU modules or AI-specific interconnects such as NVLink or CXL. - Ability to build automated test frameworks in Python or TCL, integrating lab equipment with Pandas and NumPy for correlation. - Transaction- and link-layer expertise in PCIe Gen5/6 and DDR5 beyond physical layer knowledge.

Skills: Signal Integrity (SI), system-level hardware validation, PCIe Gen5/6, DDR5, 112G/224G Ethernet, S-parameters, TDR, eye diagram analysis, Ansys HFSS, Cadence Sigrity