Senior Technical Staff Engineer - Validation (System Design) - CA - San Jose - 3850 N. First St, United States
$91,000 - $232,000 USD yearly
Originally posted 23 June 2026 by the employer.
About the role
Microchip Technology Inc. has a Senior Technical Staff Engineer - Validation (System Design) opening based in San Jose, CA, responsible for lab bring up and automation of FPGA design creation and validation. The role centers on using FPGAs to create system-level designs and developing partial reconfiguration use cases across hardware features and IP cores.
What you'll do
- Create system-level FPGA designs to bring up and debug systems in the lab, including validating system-level use cases for partial reconfiguration. - Define architecture and develop high-level system and product validation plans for new and existing silicon products. - Write and maintain RTL in Verilog, VHDL, and C code supporting regression and design re-use. - Perform board-level lab debug, failure analysis, and troubleshooting of digital logic and analog circuits on PCBs using oscilloscopes, protocol analyzers, and integrated logic analyzers. - Serve as technical expert on high-speed serial interface protocols across PHY, PCS, and Data link layers, validating technologies such as PCIe and Gigabit Ethernet. - Use AI-based tools to automate workflows and improve FPGA design and validation processes.
What you'll need
- BSEE, BSCS, or equivalent with 15+ years of experience. - Deep knowledge of FPGA architectures and hands-on experience in FPGA prototype emulation, silicon validation, and debug. - Demonstrated RTL coding experience in Verilog and VHDL, along with simulation (ModelSim) and synthesis (Synplicity) tools. - Hands-on system-level debug experience with high-speed serial protocols across PHY, PCS, and Data link layers (including PCIe Gen3/4/5 and Gigabit Ethernet), plus familiarity with 32Gbps SERDES bring up. - Board-level troubleshooting experience in a lab environment using oscilloscopes, digital analyzers, Spirent Test Center or equivalent traffic generators, and integrated logic analyzers. - Proficiency in C, C++, or object-oriented programming, alongside scripting in Python, PERL, or TCL.
Nice to have
- MSEE or MSCS. - Familiarity with high-speed SERDES controllers utilizing 32Gbps PCS/PMA across Ethernet (up to 400 Gbps), Interlaken, OTN/SONET, PON, Video interfaces (SDI, DisplayPort, HDMI), or JESD204C. - Design and debug experience with protocols including Hybrid Memory Cube, CPRI, Serial RapidIO 4.1, USB 3.0, SATA, Fibre Channel, or CoaXPress. - Experience in embedded firmware development, as well as JTAG, SVF, IEEE 1532 standards, and STAPL programming.
Skills: FPGA, lab bring up, validation, Verilog, VHDL
This role has been open 121 days — well above the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
436
|
Median days open
41 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (436 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 436 |
| Open roles in the wider Silicon Validation & Test family | 64 | 2256 · 113 employers |
| Median days open | 74 d | 41 d (+33 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: FPGA, lab bring up, validation, Verilog, VHDL
Who's hiring in this category
- AMD · 55 open roles · median 41 d
- Qualcomm · 38 open roles · median 29 d
- Micron Technology · 37 open roles · median 38 d
- NVIDIA · 25 open roles · median 24 d
- Microchip Technology (this employer) · 22 open roles · median 74 d
- Graphcore · 21 open roles · median 127 d
How we counted: 436 open Post-Silicon Validation (Silicon Validation) roles from 63 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.