Senior Technical Staff Engineer – Emulation
Architect Veloce RTL models and UVM-acceleration across EdgeAI, PCIe, Ethernet, and DDRC IP.
Originally posted 15 July 2026 by the employer.
About the role
This role is part of the FPGA Solutions Engineering team, working to architect, validate, and deliver IP cores and system-level platforms bridging hardware architecture, emulation methodologies, and firmware co-design. Technical focus centers on Veloce platforms and UVM-acceleration across EdgeAI, PCIe, Ethernet, and DDRC.
What you'll do
- Architect Veloce RTL models and UVM-acceleration for EdgeAI, PCIe, Ethernet, DDRC, and related interfaces.
- Build CAD execution flows, develop high-fidelity emulation models, Veloce XACTORs, and system-level use cases for performance and architectural validation on emulation platforms.
- Integrate hard and soft IP RTL with bare-metal firmware on emulation systems to enable shift-left solution development.
- Develop system bring-up frameworks, debug complex RTL and firmware issues, and execute hardware-software co-validation.
- Deliver technical feedback to Silicon Engineering, Software Engineering, and Marketing, while providing pre- and post-sales design support to customers and sales teams.
What you'll need
- BSEE / MSEE or equivalent technical degree.
- 10+ years of progressive experience in hardware emulation, RTL design, FPGA methodologies, or HW/SW co-verification.
- Strong proficiency with Veloce platforms, VirtuaLAB environments, UVM-acceleration, and SystemC-DPI testing methodologies.
- Proficiency in Verilog, SystemVerilog, C/C++, and RTL synthesis concepts.
- Deep understanding of high-speed IPs including PCIe, Ethernet, DDR3/4/5, AMBA AHB/APB, SERDES, and USB.
- Working knowledge of FPGA architectures (such as Microsemi, Xilinx, Altera, Lattice) and debugging physical boards.
- Foundation in DSP theory, processor architectures, or embedded processors such as ARM Cortex platforms.
Skills: hardware emulation, UVM-acceleration, Veloce, RTL design, HW/SW co-verification, PCIe, Ethernet, DDR
More semiconductor jobs: Microchip Technology jobs · Verification engineer jobs · India jobs
This role has been open 112 days — well above the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1317
|
Median days open
57 d
|
Category median salary (all employers)
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (1317 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 1317 |
| Open roles in the wider Digital Design & Verification family | 74 | 3497 · 120 employers |
| Median days open | 43 d | 57 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: hardware emulation, UVM-acceleration, Veloce, RTL design, HW/SW co-verification, PCIe
Who's hiring in this category
- Qualcomm · 117 open roles · median 49 d
- NVIDIA · 104 open roles · median 71 d
- Apple · 99 open roles · median 9 d
- AMD · 83 open roles · median 65 d
- Synopsys · 73 open roles · median 50 d
- SiFive · 58 open roles · median 63 d
How we counted: 1317 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.