Senior System Integration and Validation Engineer - CA, Santa Clara, United States
$168,000 - $310,500 USD yearly
Originally posted 10 September 2026 by the employer.
Lead system validation for GPU, SoC, and platform programs.
About the role
This role involves leading system validation, debug, and cross-functional alignment for silicon programs, sitting on the critical path of flagship builds.
What you'll do
- Own end-to-end system validation of NVIDIA GPU, SoC, and platform programs, including feature checks, PVT stress, system-stress campaigns at scale, and multi-unit fleet testing.
- Lead debug of cross-stack issues across logic, signal integrity, power delivery, firmware, and software interaction to root cause with reusable workarounds and productized fixes.
- Develop test plans, scripts, and automation for chips ahead of physical builds, translating architecture, boot flows, high-speed I/O, and power and thermal dependencies into executable coverage.
- Design and deploy AI-enabled debug and validation workflows with explicit guardrails and measurable impact on cycle time, debug velocity, or escape rate.
- Translate complex silicon and system risk into decision-ready options for technical and executive audiences.
- Partner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering.
What you'll need
- BTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering (or equivalent experience), plus 8+ years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products.
- Hands-on debug depth across silicon, board, and software boundaries, including logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior, with strong EE fundamentals across SI/PI, power delivery, and thermal, and a working understanding of GPU, CPU, or SoC architecture.
- Specific example of taking an ambiguous, multi-team failure to root-cause closure with a productized fix, and a track record of leading a project team end-to-end through a real crisis with decision points you owned.
- Demonstrated AI-driven validation workflow you built or scaled, with adoption beyond yourself and measurable impact on debug velocity, coverage, or escape rate, including guardrails you put in place.
Skills: system validation, GPU, SoC, platform programs, PVT stress, debug cross-stack issues, AI-enabled validation, high-speed I/O
This role has been open 34 days — below the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
412
|
Median days open
41 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (412 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 25 | 412 |
| Open roles in the wider Silicon Validation & Test family | 95 | 2224 · 112 employers |
| Median days open | 22 d | 41 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: system validation, GPU, SoC, platform programs, PVT stress, debug cross-stack issues, AI-enabled validation, high-speed I/O
Who's hiring in this category
- AMD · 58 open roles · median 41 d
- Micron Technology · 39 open roles · median 37 d
- Qualcomm · 37 open roles · median 27 d
- NVIDIA (this employer) · 25 open roles · median 22 d
- Graphcore · 21 open roles · median 120 d
- Microchip Technology · 20 open roles · median 70 d
How we counted: 412 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.