Senior Standard Cell Library Engineer - United States
$122,440 - $232,190 USD yearly
Originally posted 1 September 2026 by the employer.
Join Intel's Foundry Standard Cell team.
About the role
As a Senior Standard Cell Library Engineer, you will design experiments to develop, characterize, and test standard cells. You will play a critical role in enabling customers by building standard cell solutions.
What you'll do
- Define, implement, characterize, and validate design solutions for power, performance, area (PPA), manufacturability, and cost.
- Implement physical design flow aspects including standard cell circuit, layout, extraction, characterization, and optimization of timing, congestion, power, signal integrity, and reliability.
- Collaborate with standard cell collateral teams to understand design requirements and develop robust implementation and validation strategies.
- Review and validate work to ensure compliance with design, manufacturing, and quality requirements.
- Devise and run end-to-end experiments, guiding data-driven decisions across multiple audiences.
- Run end-to-end flows to generate, validate, and release custom standard cell collateral.
What you'll need
- Bachelor's degree in Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM related field.
- 2+ years of experience in standard cell layout, standard cell abstract modeling, standard cell characterization, or ASIC design and verification.
- Experience using Cadence Virtuoso, Synopsys Custom Compiler, Cadence Abstract Generator, Synopsys PrimeLib, Cadence Liberate, Synopsys Fusion Compiler, Cadence Innovus, Cadence Tempus, Synopsys PrimeTime, Synopsys HSpice, Synopsys StarRC, Synopsys ICV, Cadence Pegasus, or Siemens Calibre.
Nice to have
- Post Graduate Degree in Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM related field.
- Unix proficiency and basic software skills using csh, bash, perl, or python.
Skills: standard cell, layout, characterization, PPA, Cadence Virtuoso, Calibre
This role has been open 47 days — well below the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
60 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 659 |
| Open roles in the wider Physical Implementation family | 60 | 1440 · 110 employers |
| Median days open | 11 d | 60 d (−49 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: standard cell, layout, characterization, PPA, Cadence Virtuoso, Calibre
Who's hiring in this category
- Qualcomm · 119 open roles · median 45 d
- AMD · 63 open roles · median 24 d
- NVIDIA · 37 open roles · median 72 d
- Synopsys · 37 open roles · median 32 d
- Intel Corporation (this employer) · 36 open roles · median 11 d
- Broadcom · 30 open roles · median 97 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.