Senior Standard Cell Design Engineer - Sunnyvale, CA | St. Paul, MN, United States
Originally posted 9 October 2026 by the employer.
Join JRC's Semiconductor Technology team to lead the development of the LEAP Standard Cell Library.
About the role
This role involves driving the technical execution of the LEAP Standard Cell Library and developing radiation-hardened microelectronics.
What you'll do
- Execute the design and development of Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes.
- Generate and validate new standard cells and IP, including combinatorial logic, sequential logic, and power management cells.
- Leverage in-house software and industry-standard SPICE tools to calculate radiation-induced error rates.
- Execute advanced library characterizations to optimize Power, Performance, and Area (PPA) in harsh environments.
- Collaborate directly with external foundry partners on Multi-Product Wafer (MPW) runs and provide technical design support to customers.
- Contribute to the development of proprietary simulation software and automation scripts to improve reliability prediction.
What you'll need
- Master’s degree with 2+ years of direct industry experience, OR a Bachelor’s degree with 4+ years of experience.
- Eligibility to obtain a U.S. security clearance.
- Deep knowledge of semiconductor design methodologies and principles.
- Hands-on experience with standard cell design, circuit design, layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE).
- Demonstrated experience being involved in test-chip designs and MPW execution.
- Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.
- Extensive experience with simulation tools, specifically for library characterization.
Nice to have
- Master’s degree with 5+ years of experience, or Bachelor’s with 7+ years in industry.
- Hands-on design experience with GAA nodes (e.g., Intel 18A), including device architecture and design-rule familiarity.
- Proven background in SRAM/NVM bitcell design and/or memory compiler development.
- Practical experience with Liberate, PrimeLib, and SiSmart for characterization and modeling.
- Expertise in RHBD for SEE/SEU mitigation, plus proficiency in C++ and scripting (Python/TCL) across advanced nodes (FinFET, GAA, SOI).
Skills: standard cell design, radiation-hardened, library characterization, MPW, DRC/LVS, timing analysis
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1010
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | JRC Careers | All employers we track in this specialty (1010 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1010 |
| Open roles in the wider Digital Design & Verification family | 1 | 3176 · 114 employers |
| Median days open | 0 d | 62 d (−62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: standard cell design, radiation-hardened, library characterization, MPW, DRC/LVS, timing analysis
Who's hiring in this category
- Qualcomm · 143 open roles · median 60 d
- Synopsys · 82 open roles · median 24 d
- AMD · 73 open roles · median 35 d
- Analog Devices · 48 open roles · median 40 d
- NXP Semiconductors · 48 open roles · median 77 d
- NVIDIA · 45 open roles · median 63 d
How we counted: 1010 open Digital/RTL Design (RTL Design) roles from 97 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.