Senior Staff Test Engineer - Hsinchu City, Taiwan
Originally posted 3 August 2026 by the employer — open 38 days.
About the role
This role involves developing and optimizing test programs and methodologies for silicon semiconductor chips to ensure product quality and meet customer specifications.
What you'll do
- Develop wafer sort test programs for production or characterization on ATE or bench test platforms.
- Review testability with DFT/DFM teams to define and enhance yield and test methodologies.
- Lead test flow optimization, test time reduction, insertion removals, and yield improvement.
- Set SYL/SBL on new products using product yield history to ensure product quality.
- Work with NPI Product Engineering to drive yield improvement and test time reduction.
- Qualify and manage OSATs for capacity and competitive cost.
What you'll need
- Bachelor's degree in electrical engineering or related fields and 10 years of related professional experience OR Master's degree in electrical engineering or related fields with 5 years of experience.
- 5+ years of experience with RF/Mixed-Sign IC test.
- Experience sustaining high-speed RF products that have moved into volume production.
- Wafer sort analysis experience for analog devices up to 65GHz.
- Demonstrable experience in ATE testing and test methodology.
Nice to have
- Demonstrable experience with C / C++ /Python/Perl.
- Familiarity with test bench equipment, including Network Analyzers, Sampling Oscilloscopes, and Power Meters.
This role has been open 38 days — well above the 22-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
302
|
Median days open
22 d
|
Median salary
$154k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (302 roles · 60 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 302 |
| Open roles in the wider Silicon Validation & Test family | 54 | 1959 · 109 employers |
| Median days open | 38 d | 22 d (+16 d vs this employer) |
| Median salary (USD postings) | — | $154k |
Who's hiring in this category
- Infineon Technologies · 30 open roles · median 19 d
- Renesas Electronics · 29 open roles · median 23 d
- Qualcomm · 19 open roles · median 21 d
- AMD · 18 open roles · median 21 d
- Micron Technology · 17 open roles · median 17 d
- NVIDIA · 16 open roles · median 15 d
How we counted: 302 open Silicon Test Engineering (DFT Test) roles from 60 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.