Senior Staff Signal and Power Integrity Engineer - Pune, India
Originally posted 4 September 2026 by the employer — open 6 days.
About the role
This role involves performing signal and power integrity analysis and optimization for chip, package, and system integration. You will contribute to advanced packaging technologies like FC/InFO.
What you'll do
- Perform pre-layout and post-layout simulation flow.
- Execute SI/PI/EMC design-optimization for chip/package/system integration and electrical performance optimization.
- Develop system integration design guidelines with SI/PI total solution.
- Create simulation models and develop simulation methodology for SI/PI design.
- Use simulation and lab data to support design troubleshooting and propose corrective actions.
- Work with package design and testing teams to optimize Package and/or SI design based on simulation data.
What you'll need
- MS or PhD in Electrical Engineering.
- 10 years or above of recent Signal Integrity experience.
- Experience on package level signal and power integrity.
- Knowledge of package-level system architecture, I/O structures & topologies.
- Experience with 3D EM modeling (Ansys HFSS) and simulation (Agilent ADS or similar) software.
- Experience with signal and power integrity analysis tools (HSPICE, Sigrity tools, PowerDC etc).
Skills: signal integrity, power integrity, SI/PI/EMC, package-level, 3D EM modeling, HSPICE, Sigrity
This role has been open 6 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lattice Semiconductor | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 4 | 1317 · 100 employers |
| Median days open | 6 d | 91 d (−85 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: signal integrity, power integrity, SI/PI/EMC, package-level, 3D EM modeling, HSPICE
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.