Senior/Staff/Principal IC Layout Engineer – Optical Engine Silicon - Singapore

Originally posted 24 September 2026 by the employer.

About the role

This role involves owning layout for electronic ICs (EICs) and photonic ICs (PICs) at Lumilens, focusing on high-speed analog blocks where layout significantly impacts design.

What you'll do

• Own floorplan and layout for high-speed analog and mixed-signal blocks: TIAs, drivers, SerDes front ends, PLL and clocking, references and bias.
• Execute device-level matching and symmetry including common-centroid, dummies, shielding, guard rings, and substrate isolation.
• Route high-speed signal paths with control over impedance, coupling, and return paths; lay out passive and electromagnetic structures.
• Own chip finishing including pad ring, bump and pillar maps, seal ring, density fill, and top-level assembly through tape out.
• Drive parasitic-aware layout, iterating with designers on extraction results and closing the loop between schematic assumptions and layout delivery.
• Support PIC layout for waveguide and curvilinear structures, and own the EIC-PIC integration, including micro-bump and pillar alignment and interposer interfaces.

What you'll need

• Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.
• 8+ years in custom analog, RF, or high-speed mixed-signal IC layout, including multiple tape outs.
• Expert-level Cadence Virtuoso, including Layout XL and constraint-driven flows.
• Deep parasitic awareness.
• Working command of electromigration and IR drop fundamentals.
• Electromagnetics fundamentals for on-chip structures including inductors, transformers, transmission lines, coupling, and shielding.
• Physical verification fluency: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.

Nice to have

• SiGe BiCMOS layout experience.
• Advanced FinFET CMOS layout at 7nm and below.
• Photonic IC layout exposure: waveguide routing, curvilinear geometry, and photonics PDK design rules.
• Hands-on silicon photonics layout on a foundry platform, including PCell development in Virtuoso SKILL or Python-based photonic layout tools (gdsfactory, KLayout, IPKISS).
• Understanding of how layout drives photonic performance.
• 2.5D and 3D integration, interposers, micro-bump and copper pillar arrays, and co-packaged optics assemblies.
• Layout for optical front ends specifically: TIA, modulator driver, or high-speed serial link blocks.
• Experience standing up layout methodology for a product line in its first generation.
• Scripting for layout automation: SKILL, Python, or both.

Skills: high-speed analog layout, PIC layout, waveguide routing, Cadence Virtuoso, DRC/LVS