Senior Staff Integration Design Engineer - San Jose, CA, United States

Originally posted 6 October 2026 by the employer.

This role integrates DDR PHY into shared HPIO sectors for FPGA platforms.

About the role

This role involves integrating IP blocks, including DDR PHY, into shared HPIO sectors to build sector- and full-chip-level views for FPGA platforms. The work utilizes both digital design flows, such as synthesis, static timing analysis (STA), and design for test (DFT), and custom physical/custom cell design flows.

What you'll do

• Integrate IP blocks, including DDR PHY, into shared HPIO sectors for FPGA platforms.
• Create and maintain sector-level design constraints (SDC), including flat SDC generation for STA.
• Run and maintain the digital implementation flow for the sector, including RTL updates, synthesis, logical equivalence checking (LEC), STA, and DFT scan integration.
• Support custom/physical design integration tasks for the sector, including custom cell design, parasitic (SPEF) extraction, and clock-critical signal routing/shielding review.
• Track and resolve sector-level design issues through the engineering issue tracker (JIRA) and publish regular status updates to cross-functional stakeholders.
• Run full design verification (DV) regressions and sign-off checks for each sector release, and manage version-controlled releases of sector netlists, SDC, and related collateral.
• Collaborate with IP Design, Product Engineering, and Test teams to integrate IP-level power data into full-chip power models.
• Review and cross check IP design's SPICE-level circuit simulation and PnR power results to characterize static and dynamic power across process, voltage, and temperature corners.

What you'll need

• BS or MS in Electronics/Computer/Electrical Engineering.
• 15+ years of experience in ASIC, SoC, or FPGA design and product-development.
• In-depth experience in Custom and Digital Design Implementation for IP/sector integration.
• Expertise in Verilog and System Verilog.
• Expertise in Digital Design Flow, including RTL coding and verification, Lint check, elaboration/compilation, synthesis, equivalence check, SDC, and DFT flow and ATPG generation.
• Expertise in Custom Design Flow, including semiconductor principles and transistor-level analysis, industry standard tools for schematic and layout entry (Cadence Virtuoso), and characterization, performance, and power simulations (SPICE preferred).
• Expertise in coding/scripting (Perl, TCL, Shell, Skill, Python).
• Familiarity with issue tracking and release workflows (e.g., JIRA) in a hardware engineering environment.
• Working knowledge of SPICE-class circuit simulation, CMOS low-power design concepts (leakage, dynamic power, corner analysis), and correlating simulation results to silicon/bench measurement data.

Nice to have

• Experience in FPGA/CPLD design and integration.
• Experience in IP and full-chip functional verification.
• Experience in project leadership and product development cycle (planning, resourcing, tapeout, silicon characterization/validation).
• Experience with multiple process nodes/foundries (e.g., TSMC, Samsung).

Skills: FPGA, DDR PHY, synthesis, STA, DFT