Senior Staff Formal Verification Engineer - San Diego, California, United States of America
$195,200 - $325,000 USD yearly
Originally posted 12 January 2026 by the employer.
About the role
This role involves developing formal verification testbenches, implementing hardware emulation, and verifying complex designs in the GPU ASICS Engineering group.
What you'll do
- Synthesize Verilog RTL and create models to compile onto emulators such as Veloce, Palladium, and ZeBu, or FPGA platforms. - Develop hardware emulator implementations focusing on design partitioning, synthesis, place and route, timing analysis, and run-time performance. - Drive failure debug on emulators in collaboration with design and software driver teams for test planning. - Work on third-party IP integration, system-level debugging, system-level RTL simulation, and design verification. - Support chip bring-up, post-silicon debug, and the debug of functional and timing models. - Collaborate with tool vendors to refine methodologies and optimize area and performance for synthesized FPGA RTL.
What you'll need
- Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with 6+ years of relevant engineering experience, or a Master's degree with 5+ years of experience, or a PhD with 4+ years of experience. - Proficiency in formal tools, formal verification methodologies, assertion development, and design debug. - Experience with Verilog RTL synthesis, design partitioning, and timing analysis. - Experience compiling designs to hardware emulators (such as Veloce, Palladium, or ZeBu) or FPGA platforms.
Nice to have
- Experience with emulation platforms, platform bring-up, digital design verification, and waveform viewers. - Hands-on experience with hardware emulators (Palladium, ZeBu, Veloce) or FPGA systems based on Xilinx or Altera FPGAs. - Knowledge of emulation methodologies including in-circuit emulation, hybrid systems, or simulation acceleration. - Design verification experience with UVM and SystemVerilog. - Knowledge of GPU, CPU, DDR, or Bus architectures. - Programming skills in C and C++, alongside scripting in Python, Tcl, or Perl. - Familiarity with vendor emulation tools, Xilinx tools, and synthesis tools.
Skills: Verilog RTL, emulators, FPGA platforms, design partitioning, synthesis, timing analysis
This role has been open 200 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1259
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1259 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 118 | 1259 |
| Open roles in the wider Digital Design & Verification family | 420 | 3310 · 115 employers |
| Median days open | 45 d | 65 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Verilog RTL, emulators, FPGA platforms, design partitioning, synthesis, timing analysis
Who's hiring in this category
- Qualcomm (this employer) · 120 open roles · median 44 d
- NVIDIA · 93 open roles · median 65 d
- AMD · 92 open roles · median 54 d
- Synopsys · 65 open roles · median 40 d
- SiFive · 55 open roles · median 82 d
- Cadence Design Systems · 52 open roles · median 124 d
How we counted: 1259 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.