Senior Staff Formal Verification Applications Engineer
Synopsys
img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Sunnyvale, California, United States
14 days ago
Applications & FAE
Originally posted 27 September 2026 by the employer.
Work directly with customers deploying VC Formal across complex semiconductor designs.
About the role
This role involves leading formal verification methodology deployment at customer sites, working hands-on to integrate VC Formal into existing flows.
What you'll do
- Lead formal verification methodology deployment at customer sites to integrate VC Formal into existing flows.
- Assess customer design environments, identify high-value blocks for formal analysis, and define metrics.
- Debug and resolve tool performance issues by analyzing design complexity and optimizing assertion modeling.
- Develop and deliver technical training on VC Formal features, releases, and best practices.
- Collaborate with Synopsys R&D and product engineering to communicate customer requirements and influence the product roadmap.
- Apply formal verification techniques across property checking, datapath verification, sequential equivalence checking, formal coverage analysis, and connectivity checking.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
- 6+ years of hands-on experience in formal verification, including property checking, sequential equivalence checking, formal coverage, and connectivity checking.
- Deep expertise with formal verification tools, including VC Formal or equivalent platforms.
- Strong understanding of SystemVerilog Assertions (SVA), formal testbench modeling, and abstraction techniques.
- Proven ability to debug tool performance issues, analyze convergence problems, and optimize formal runs for large, complex designs.
- Experience working directly with customers or cross-functional engineering teams in a technical consulting, applications engineering, or field engineering role.
- Solid grasp of RTL design, verification methodologies, and the semiconductor development lifecycle from architecture through tapeout.
Skills: formal verification, VC Formal, SVA, assertion modeling, verification closure
Synopsys
img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Sunnyvale, California, United States
On-site
14 days ago