Senior Staff Engineer Pre-Silicon Verification AMS - Austin, TX
$117,840 - $162,030 USD yearly
Originally posted 5 June 2026 by the employer.
About the role
As a Senior Staff Engineer Pre-Silicon Verification AMS in the Research & Development team, you will generate behavioral models and execute pre-silicon verification for Engineering and Production ICs.
What you'll do
- Generate VerilogAMS and SystemVerilog models and correlate results with schematic-level performance using test benches. - Coordinate with team members on design entry, development, and implementation of custom AMS behavioral models and schematic netlisting. - Generate tests and perform verification of mixed-signal designs utilizing Cadence ADE Explorer and the Xcelium suite of tools. - Generate simulation workbenches and interpret results to verify compliance with device-level and system-level requirements. - Contribute to, support, and perform verification of DFT plans including digital scan chain testing. - Support and verify functionality performances, ATE, and bench testability of Production ICs.
What you'll need
- BSEE/ME or equivalent with 3+ years of experience. - Experience with Cadence Virtuoso and Xcelium Tool Suite driven by hierarchy configurations. - Experience compiling, elaborating, and running mixed-signal simulations in both ADE Explorer and Xcelium. - Solid understanding of analog Spectre simulation and associated AMS modeling of analog circuit blocks. - Understanding of analog design techniques, signal flow, and boundaries between analog and digital domains. - Conversance in Verilog, Python, C, and C++ with the ability to generate simple scripts.
Skills: VerilogAMS, SystemVerilog, Cadence ADE Explorer, Xcelium, mixed-signal simulations
This role has been open 200 days — below the 202-day median for Design Verification roles.
Design Verification · Mixed Signal
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Open roles in category
52
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Median days open
202 d
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Median salary
—
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (52 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 52 |
| Open roles in the wider Digital Design & Verification family | 90 | 3310 · 115 employers |
| Median days open | 200 d | 202 d (−2 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: VerilogAMS, SystemVerilog, Cadence ADE Explorer, Xcelium, mixed-signal simulations
Who's hiring in this category
- Cadence Design Systems · 12 open roles · median 214 d
- Qualcomm · 6 open roles · median 199 d
- Infineon Technologies (this employer) · 5 open roles · median 199 d
- Retym · 5 open roles · median 94 d
- NVIDIA · 4 open roles · median 199 d
- Microchip Technology · 2 open roles · median 221 d
How we counted: 52 open Design Verification (Mixed Signal) roles from 20 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.